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2008 International Conference on Field Programmable Logic and Applications最新文献

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The effect of sparse switch patterns on the area efficiency of multi-bit routing resources in field-programmable gate arrays 稀疏开关模式对现场可编程门阵列中多比特路由资源区域效率的影响
2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1109/FPL.2008.4629975
Ping Chen, A. Ye
{"title":"The effect of sparse switch patterns on the area efficiency of multi-bit routing resources in field-programmable gate arrays","authors":"Ping Chen, A. Ye","doi":"10.1109/FPL.2008.4629975","DOIUrl":"https://doi.org/10.1109/FPL.2008.4629975","url":null,"abstract":"The increased use of multi-bit processing elements such as digital signal processors, multipliers, multi-bit addressable memory cells, and CPU cores has presented new opportunities for Field-Programmable Gate Array (FPGA) architects to utilize the regularity of multi-bit signals to increase the area efficiency of FPGAs. In particular, configuration memory sharing has been traditionally used to exploit multi-bit regularity for area. We observe that the process of creating configuration memory sharing routing resources often leads to the use of much sparser switch patterns for connecting multi-bit elements to their routing tracks. In this work, we empirically evaluate the effect of these sparse switch patterns on the area efficiency of FPGAs. It is shown that the sparse switch patterns alone contribute significantly to the area reduction observed in configuration memory sharing FPGAs. In particular, our experiments show that, without configuration memory sharing, sparse switch patterns can reduce the implementation area of multi-bit routing resources by 10.4% while configuration memory sharing contributes to an additional 1.2% in area savings. The observation holds over a wide range of connection block flexibility values and demonstrates that efficient switch pattern designs can be effectively used to increase the area efficiency of FPGA routing resources.","PeriodicalId":137963,"journal":{"name":"2008 International Conference on Field Programmable Logic and Applications","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121976208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
CVC: The C to RTL compiler for callback-based verification model CVC:基于回调的验证模型的C到RTL编译器
2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1109/FPL.2008.4629993
Yasuhiro Ito, Yutaka Sugawara, M. Inaba, K. Hiraki
{"title":"CVC: The C to RTL compiler for callback-based verification model","authors":"Yasuhiro Ito, Yutaka Sugawara, M. Inaba, K. Hiraki","doi":"10.1109/FPL.2008.4629993","DOIUrl":"https://doi.org/10.1109/FPL.2008.4629993","url":null,"abstract":"Model-based verification is extensively begin used for accelerating the development of embedded system. However, by this approach, a model and actual RTL are required to be implemented separately, which increases the time required to ensure the equivalence of virtual models and actual hardware. To reduce the costs incurred in separate implementations, we propose to directly generate RTL from verification model used in CoMET, which is a callback-based verification environment. We design and implement CVC, a compiler used for generating RTL, using a callback-based verification model described in a subset of the C language; we impose a restriction on CVC to describe the callback efficiently. Our method enables developers to implement the complete RTL without any compromises in the RTL performance just after the verification of the callback-based model is completed.","PeriodicalId":137963,"journal":{"name":"2008 International Conference on Field Programmable Logic and Applications","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127122191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
ReCoBus-Builder — A novel tool and technique to build statically and dynamically reconfigurable systems for FPGAS ReCoBus-Builder是一种新颖的工具和技术，用于构建静态和动态可重构的fpga系统
2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1109/FPL.2008.4629918
Dirk Koch, Christian Beckhoff, J. Teich
{"title":"ReCoBus-Builder — A novel tool and technique to build statically and dynamically reconfigurable systems for FPGAS","authors":"Dirk Koch, Christian Beckhoff, J. Teich","doi":"10.1109/FPL.2008.4629918","DOIUrl":"https://doi.org/10.1109/FPL.2008.4629918","url":null,"abstract":"In this paper, we present the ReCoBus-builder tool chain that simplifies the generation of dynamically reconfigurable systems to almost a push-button process. The generated systems provide one or more resource areas that will be used by different partially reconfigurable modules at runtime. It is possible to integrate multiple partially reconfigurable modules into the same resource area at the same time and these modules can communicate via a fixed bus infrastructure or dedicated point-to-point links with other parts of the system. This allows building encapsulated modules that will be integrated into the system by linking together bitstreams at runtime. We will demonstrate that bitstream linking can further be used to speed up the design process of static only systems by eliminating long synthesis runs or place and route steps, when only small portions of a design are exchanged.","PeriodicalId":137963,"journal":{"name":"2008 International Conference on Field Programmable Logic and Applications","volume":"73 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121132125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 137
Enhancing ADC resolution through Field Programmable Analog Array dynamic reconfiguration 通过现场可编程模拟阵列动态重构提高ADC分辨率
2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1109/FPL.2008.4630027
D. Morales, Antonio García, A. Palma, M. Carvajal, Encarnación Castillo, L. F. Capitán-Vallvey
{"title":"Enhancing ADC resolution through Field Programmable Analog Array dynamic reconfiguration","authors":"D. Morales, Antonio García, A. Palma, M. Carvajal, Encarnación Castillo, L. F. Capitán-Vallvey","doi":"10.1109/FPL.2008.4630027","DOIUrl":"https://doi.org/10.1109/FPL.2008.4630027","url":null,"abstract":"This work describes an analog reconfiguration technique for acquisition and processing of analog sensor signals that involves field programmable analog arrays (FPAAs) and field programmable gate arrays (FPGAs). The main objective is to exploit their natural reconfiguration capabilities that allow the increase of the analog-to-digital conversion (ADC) resolution and an adaptive post processing of the digital signal. This work is completed by the demonstration of this technique with an NTC temperature sensor signal, increasing the ADC resolution. The proposed system acquires the analog signal with filtering, amplifications and ADC being performed on the FPAA, while dynamically tuning the analog conditioning on the FPAA; after that, the FPGA processes the digital signal and delivers the final result to the end user, also involving the use of an embedded PicoBlaze.","PeriodicalId":137963,"journal":{"name":"2008 International Conference on Field Programmable Logic and Applications","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126674618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Modeling recursion data structures for FPGA-based implementation 基于fpga实现的递归数据结构建模
2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1109/FPL.2008.4629900
Spyridon Ninos, A. Dollas
{"title":"Modeling recursion data structures for FPGA-based implementation","authors":"Spyridon Ninos, A. Dollas","doi":"10.1109/FPL.2008.4629900","DOIUrl":"https://doi.org/10.1109/FPL.2008.4629900","url":null,"abstract":"Recursion is a powerful technique used to solve problems with repeating patterns, and is a fundamental structure in software. To date there is no known general way to apply a recursive solution to reconfigurable hardware; it is considered difficult to implement, of low performance and resource-intensive. In this paper we extend previous results on hardware structures for recursion by V. Sklyarov, and we demonstrate that recursion can be efficiently implemented in a general way on FPGAs. We show that our general, non-optimized architecture presents approximately 3 times speedup against optimized software algorithm implementations. It also shows 75% speedup, at least 40% lower area utilization, and at the same time it is simpler, less designer time consuming and more general vs. previously published hardware implementations.","PeriodicalId":137963,"journal":{"name":"2008 International Conference on Field Programmable Logic and Applications","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116701040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
EMMA - A suggestion for an embedded multi-precision multiplier array for FPGAs 一种用于fpga的嵌入式多精度乘法器阵列
2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1109/FPL.2008.4629977
O. Pfänder, H. Pfleiderer
{"title":"EMMA - A suggestion for an embedded multi-precision multiplier array for FPGAs","authors":"O. Pfänder, H. Pfleiderer","doi":"10.1109/FPL.2008.4629977","DOIUrl":"https://doi.org/10.1109/FPL.2008.4629977","url":null,"abstract":"This paper presents a non-monolithic top-down reconfigurable multiplier suitable for embedding in an FPGA structure. It is constructed of four individual partitions that can operate as separate multipliers but also concatenate to form a superior multiplier with increased precision and sign handling ability. The number of possible operation modes is limited in order to keep the reconfiguration overhead low. A small set of control signals determines behavior and mode selection. Inactive partitions are disconnected from the supply to save power. EMMA (Embedded Multi-precision Multiplier Array) can compute signed twopsilas complement numbers at up to 32 times 16-bit precision when all partitions are active and concatenated, or up to four separate 16 times 8-bit multiplications running simultaneously.","PeriodicalId":137963,"journal":{"name":"2008 International Conference on Field Programmable Logic and Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130693648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
BOUNCE, a new approach to measure sub-nanosecond time intervals 一种测量亚纳秒时间间隔的新方法
2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1109/FPL.2008.4629996
R. Joost, R. Salomon
{"title":"BOUNCE, a new approach to measure sub-nanosecond time intervals","authors":"R. Joost, R. Salomon","doi":"10.1109/FPL.2008.4629996","DOIUrl":"https://doi.org/10.1109/FPL.2008.4629996","url":null,"abstract":"Tapped delay lines are chain-like structures, which are able to measure short time intervals. Due to their homogeneous structure, they are particularly suited for being implemented on field-programmable gate arrays. But unfortunately, the attainable resolution in time is inherently limited to the average processing speed of the chain elements. As an alternative, this paper proposes a new architecture, called BOUNCE in which all processing elements run in parallel. With its inherent parallelism, BOUNCE yields a resolution that depends on the variation, i.e., the differences, among the elementspsila processing speeds. The first prototype was implemented on an ALTERA StratixII 2S60 board. Even though this board is clocked at only 85 MHz, the prototype yields a resolution of about 150 ps.","PeriodicalId":137963,"journal":{"name":"2008 International Conference on Field Programmable Logic and Applications","volume":"7 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130930455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Creating unique identifiers on field programmable gate arrays using natural processing variations 使用自然处理变化在现场可编程门阵列上创建唯一标识符
2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1109/FPL.2008.4630013
J. Crouch, Hiren J. Patel, Yong C. Kim, R. Bennington
{"title":"Creating unique identifiers on field programmable gate arrays using natural processing variations","authors":"J. Crouch, Hiren J. Patel, Yong C. Kim, R. Bennington","doi":"10.1109/FPL.2008.4630013","DOIUrl":"https://doi.org/10.1109/FPL.2008.4630013","url":null,"abstract":"In this paper, we proposes the concept of creating a circuit identifier, or digital fingerprint, for field programmable gate arrays (FPGAs). The digital fingerprint is a function of the natural variations in the semiconductor manufacturing process that cannot be duplicated or forged. The proposed digital fingerprint allows the use of any arbitrary of nodes internal to the circuit or the circuit outputs as monitoring locations. Changes in the signal on a selected node or output can be quantified digitally over a period of time or at a specific instance of time. Two monitoring methods are proposed, one using cumulative observation of the nodes and the other samples the nodes based on a signal transition. Two monitoring methods were validated on a small sample of twenty Xilinxreg Virtex-II Pro FPGAs, where both methods successfully created unique identifiers for each FPGA.","PeriodicalId":137963,"journal":{"name":"2008 International Conference on Field Programmable Logic and Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129686930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A high performance microprocessor with DSP extensions optimized for the Virtex-4 FPGA 一种高性能微处理器，带有针对Virtex-4 FPGA优化的DSP扩展
2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1109/FPL.2008.4630018
A. Ehliar, Per Karlström, Dake Liu
{"title":"A high performance microprocessor with DSP extensions optimized for the Virtex-4 FPGA","authors":"A. Ehliar, Per Karlström, Dake Liu","doi":"10.1109/FPL.2008.4630018","DOIUrl":"https://doi.org/10.1109/FPL.2008.4630018","url":null,"abstract":"As the use of FPGAs increases, the importance of highly optimized processors for FPGAs will increase. In this paper we present the microarchitecture of a soft microprocessor core optimized for the Virtex-4 architecture. The core can operate at 357 MHz, which is significantly faster than Xilinxpsila Microblaze architecture on the same FPGA. At this frequency it is necessary to keep the logic complexity down and this paper shows how this can be done while retaining sufficient functionality for a high performance processor.","PeriodicalId":137963,"journal":{"name":"2008 International Conference on Field Programmable Logic and Applications","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129782779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Decimal multiplier on FPGA using embedded binary multipliers 十进制乘法器在FPGA上使用嵌入式二进制乘法器
2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1109/FPL.2008.4629931
H. Neto, M. Véstias
{"title":"Decimal multiplier on FPGA using embedded binary multipliers","authors":"H. Neto, M. Véstias","doi":"10.1109/FPL.2008.4629931","DOIUrl":"https://doi.org/10.1109/FPL.2008.4629931","url":null,"abstract":"Decimal arithmetic has become a major necessity in computer arithmetic operations associated with human-centric applications, like financial and commercial, because the results must match exactly those obtained by human calculations. The relevance of decimal arithmetic has become evident with the revision of the IEEE-754 standard to include decimal floating-point support. There are already a variety of IP cores available for implementing binary arithmetic accelerators in FPGAs. Thus far, however, little work has been done with regard to implementing cores that work with decimal arithmetic. In this paper, we introduce a novel approach to the design of a decimal multiplier in FPGA using the embedded arithmetic blocks and a novel method for binary to BCD conversion. The proposed circuits were implemented in a Xilinx Virtex 4sx35ff877-12 FPGA. The results indicate that the proposed binary to BCD converter is more efficient than the traditional shift and add-3 algorithm and that the proposed decimal multiplier is very competitive when compared to decimal multipliers implemented with direct manipulation of BCD numbers.","PeriodicalId":137963,"journal":{"name":"2008 International Conference on Field Programmable Logic and Applications","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123333799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
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