2006 6th International Workshop on System on Chip for Real Time Applications最新文献_第3页

Development of Metal Inspection System Exploiting Magnetoresistive Sensors 基于磁阻传感器的金属检测系统的研制

2006 6th International Workshop on System on Chip for Real Time Applications Pub Date : 2006-12-01 DOI: 10.1109/IWSOC.2006.348226

Ibrahim Elshafiey, Ashraf Mohra

引用次数: 1

Effects of Etching Holes on Capacitance and Tuning Range in MEMS Parallel Plate Variable Capacitors 蚀刻孔对微机电系统并联板可变电容器电容和调谐范围的影响

2006 6th International Workshop on System on Chip for Real Time Applications Pub Date : 2006-12-01 DOI: 10.1109/IWSOC.2006.348240

A. Elshurafa, E. El-Masry

引用次数: 15

SoC Design Quality, Cycletime, and Yield Improvement Through DfM 通过DfM改进SoC设计质量、周期和良率

2006 6th International Workshop on System on Chip for Real Time Applications Pub Date : 2006-12-01 DOI: 10.1109/IWSOC.2006.348270

J. Cetin, A. Balasinski

{"title":"SoC Design Quality, Cycletime, and Yield Improvement Through DfM","authors":"J. Cetin, A. Balasinski","doi":"10.1109/IWSOC.2006.348270","DOIUrl":"https://doi.org/10.1109/IWSOC.2006.348270","url":null,"abstract":"Technology, CAD, and design are increasingly more challenged by design-for-manufacturability rules and guidelines required to improve pattern transfer quality to the reticle and silicon wafer. One key reason for this challenge is the variability of the layout, which for SoC designs beyond the 100 nm technology node should no longer be subject only to short range design rule checks concerning individual layout features. To include the impact of medium and long-range pattern interactions (across-die or exposure field) into the design process, one should change layout architecture methodology distributed so far among technology, CAD, and design groups and using manual drawing techniques or semi-automated tools with different quality standards. This task becomes even more important for the SoC layout for analog/RF applications where signal propagation is sensitive to device matching requirements and capacitive coupling. At that point, IC designer had two options to control the layout freedom: by enforcing new, more restrictive design rules or by using parameterized layout based on standard cells proven on silicon, including all electrically extracted RET, OPC, and dummy features. In this work, it was shown that the standardized layout is the preferred option leading to the improved quality, reduced cycletime, and higher yields","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114237046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Hardware/Software Co-Design of RTOS-Based Platforms 基于rtos平台的软硬件协同设计

2006 6th International Workshop on System on Chip for Real Time Applications Pub Date : 2006-12-01 DOI: 10.1109/IWSOC.2006.348271

M. H. El-Malaki, M. El-Kharashi, S. Hammad, Ashraf Salem, A. Wahdan

引用次数: 1

FPGA-Based Low-level CAN Protocol Testing 基于fpga的低级CAN协议测试

2006 6th International Workshop on System on Chip for Real Time Applications Pub Date : 2006-12-01 DOI: 10.1109/IWSOC.2006.348233

M. Mostafa, M. Shalan, S. Hammad

引用次数: 6

Fragmentation Aware Placement in Reconfigurable Devices 可重构设备中碎片感知放置

2006 6th International Workshop on System on Chip for Real Time Applications Pub Date : 2006-12-01 DOI: 10.1109/IWSOC.2006.348261

Ahmed Abou ElFarag, H. M. El-Boghdadi, S. Shaheen

引用次数: 4

An FPGA Implementation of a Hopfield Optimized Block Truncation Coding Hopfield优化块截断编码的FPGA实现

2006 6th International Workshop on System on Chip for Real Time Applications Pub Date : 2006-12-01 DOI: 10.1109/IWSOC.2006.348230

S. Saif, H. M. Abbas, S. Nassar, A. Wahdan

引用次数: 3

Hardware Software Partitioning using Particle Swarm Optimization Technique 基于粒子群优化技术的硬件软件划分

2006 6th International Workshop on System on Chip for Real Time Applications Pub Date : 2006-12-01 DOI: 10.1109/IWSOC.2006.348234

Mohamed B. Abdelhalim, A. E. Salama, S.E.-D. Habib

{"title":"Hardware Software Partitioning using Particle Swarm Optimization Technique","authors":"Mohamed B. Abdelhalim, A. E. Salama, S.E.-D. Habib","doi":"10.1109/IWSOC.2006.348234","DOIUrl":"https://doi.org/10.1109/IWSOC.2006.348234","url":null,"abstract":"In this paper the authors investigate the application of the particle swarm optimization (PSO) technique for solving the hardware/software partitioning problem. The PSO is attractive for the hardware/software partitioning problem as it offers reasonable coverage of the design space together with O(n) main loop's execution time, where n is the number of proposed solutions that will evolve to provide the final solution. The authors carried out several tests on a hypothetical, relatively-large hardware/software partitioning problem using the PSO algorithm as well as the genetic algorithm (GA), which is another evolutionary technique. The authors found that PSO outperforms GA in the cost function and the execution time. For the case of unconstrained design problem, the authors tested several hybrid combinations of PSO and GA algorithm; including PSO then GA, GA then PSO, GA followed by GA, and finally PSO followed by PSO. We found that a PSO followed by GA algorithm gives small or no improvement at all, while a GA then PSO algorithm gives the same results as the PSO alone. The PSO algorithm followed by another PSO round gave the best result as it allows another round of domain exploration. The second PSO round assign new randomized velocities to the particles, while keeping best particle positions obtained in the first round. The paper proposes to name this successive PSO algorithm as the re-excited PSO algorithm","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125746118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Analysis Design and Simulation of a Three-Phase Three-Level Nine Switches Inverter Using Space Vector Modulation 空间矢量调制三相三电平九开关逆变器的分析、设计与仿真

2006 6th International Workshop on System on Chip for Real Time Applications Pub Date : 2006-12-01 DOI: 10.1109/IWSOC.2006.348225

E. Mahrous, N. Rahim, P. Hew

引用次数: 1

SoC Session Level Modeling using Java 使用Java的SoC会话级建模

2006 6th International Workshop on System on Chip for Real Time Applications Pub Date : 2006-12-01 DOI: 10.1109/IWSOC.2006.348273

S. Aly, A. Salem

引用次数: 0