2006 6th International Workshop on System on Chip for Real Time Applications最新文献_第4页

FPGA Based Implementation of MSOVA for CDMA2000 Turbo Decoder 基于FPGA的CDMA2000 Turbo解码器MSOVA实现

2006 6th International Workshop on System on Chip for Real Time Applications Pub Date : 2006-12-01 DOI: 10.1109/IWSOC.2006.348268

A.M. Ismail, M. Nafie

引用次数: 2

A Benchmark Approach for Compilers in Reconfigurable Hardware 可重构硬件中编译器的基准测试方法

2006 6th International Workshop on System on Chip for Real Time Applications Pub Date : 2006-12-01 DOI: 10.1109/IWSOC.2006.348220

J. J. Lopes, J.S. Luiz, E. Marques, J. Cardoso

{"title":"A Benchmark Approach for Compilers in Reconfigurable Hardware","authors":"J. J. Lopes, J.S. Luiz, E. Marques, J. Cardoso","doi":"10.1109/IWSOC.2006.348220","DOIUrl":"https://doi.org/10.1109/IWSOC.2006.348220","url":null,"abstract":"High-performance FPGA accelerating software applications are a growing demand in fields as communications, image processing, and scientific computing among others. Moreover, as the cost per gate of FPGAs declines, embedded and high-performance systems designers are being presented with new opportunities for creating accelerated software applications using FPGA-based programmable hardware platforms. Powerful high-level language to RTL generators are now emerging. One of the promises of these tools is to allow software and systems engineers to implement algorithms quickly in a familiar language and target the design to a programmable device. The generators available today support syntaxes with different degrees of fidelity to the original language. This paper focuses on the efficient use of C to RTL generators that have a high degree of fidelity to the original C language. The objective of this project is to study some tools that starting from languages of high level as ANSI-C, and generate FPGA accelerating software applications automatically. In this paper are presented tools and partial results of the hardware generated by them","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114315323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Call Admission Control for ATM System using Fuzzy Control Approach 基于模糊控制的ATM系统呼叫接纳控制

2006 6th International Workshop on System on Chip for Real Time Applications Pub Date : 2006-12-01 DOI: 10.1109/IWSOC.2006.348265

H. El-Madbouly, Mohamed Hamdy

引用次数: 0

Low Power Cache Architecture 低功耗缓存架构

2006 6th International Workshop on System on Chip for Real Time Applications Pub Date : 2006-12-01 DOI: 10.1109/IWSOC.2006.348253

M. Nakkar, N. Ahmed

引用次数: 2

Parallel Processing on FPGAs: The Effect of Profiling on Performance fpga的并行处理:分析对性能的影响

2006 6th International Workshop on System on Chip for Real Time Applications Pub Date : 2006-12-01 DOI: 10.1109/IWSOC.2006.348232

Xiaoguang Li, S. Areibi, R. Dony

{"title":"Parallel Processing on FPGAs: The Effect of Profiling on Performance","authors":"Xiaoguang Li, S. Areibi, R. Dony","doi":"10.1109/IWSOC.2006.348232","DOIUrl":"https://doi.org/10.1109/IWSOC.2006.348232","url":null,"abstract":"The processing elements, logic resources, and on-chip block RAMs of modern FPGAs can not only be used for prototyping custom hardware modules, but also for parallel processing purposes by implementing multiple processors for a single task. This paper compares the performance of a single-processor implementation with two types of dual-processor implementations for a widely used radix-2 n-point FFT algorithm (Kooley and Tuckey, 1965) in terms of processing speed and FPGA resource utilization. In the first dual-processor implementation, the partitioning is performed based on the computation complexity - O(nlog(n)) of the radix-2 FFT algorithm. In the second implementation, the partitioning is based on a detailed profiling procedure applied to each line of the code in the single-processor implementation. Results obtained show that the speedup of the first dual-processor implementation is on average 1.3times faster than the single-processor implementation, whereas the second dual-processor implementation is about 1.9times faster which is very close to the expected speedup. This result shows that detailed profiling is crucial in identifying the bottlenecks of an algorithm (i.e., all the factors are taken into consideration) and consequently the algorithm can be efficiently mapped on a multiprocessor system based on the correct decision","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121289580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A Distributed and Shared Register File for a Multiprocessor-on-Chip to Support Real-Time Applications 支持实时应用的多处理器片上分布式和共享寄存器文件

2006 6th International Workshop on System on Chip for Real Time Applications Pub Date : 2006-12-01 DOI: 10.1109/IWSOC.2006.348239

N. Tabrizi, N. Bagherzadeh

引用次数: 1

On-Line Test Vector Generation from Temporal Regular Expressions 从时间正则表达式生成在线测试向量

2006 6th International Workshop on System on Chip for Real Time Applications Pub Date : 2006-12-01 DOI: 10.1109/IWSOC.2006.348223

Y. Oddos, K. Morin-Allory, D. Bomone

引用次数: 3

Architectural Design and Implementation of an FPGA Softcore Based Speech Recognition System 基于FPGA软核的语音识别系统体系结构设计与实现

2006 6th International Workshop on System on Chip for Real Time Applications Pub Date : 2006-12-01 DOI: 10.1109/IWSOC.2006.348263

Kisun You, Hyun-Sub Lim, Wonyong Sung

{"title":"Architectural Design and Implementation of an FPGA Softcore Based Speech Recognition System","authors":"Kisun You, Hyun-Sub Lim, Wonyong Sung","doi":"10.1109/IWSOC.2006.348263","DOIUrl":"https://doi.org/10.1109/IWSOC.2006.348263","url":null,"abstract":"In spite of ever increasing logic capacity of FPGAs, the implementation of a large vocabulary speech recognition system encounters insufficient I/O bandwidth and internal memory capacity problems. In this paper, a speech recognition system architecture was described based on a softcore with hardware accelerators for the emission probability computation and the Viterbi beam search. The hardware accelerator for emission probability computation is equipped with the internal memory to effectively capture the access pattern of the acoustic model data which depend on the language model. The optimal memory configuration is determined by the proposed data partitioning strategy. The developed system has been implemented on a Xilinx Virtex-4 FPGA with MicroBlaze softcore processor along with various peripherals. The experimental results show that the proposed architecture speeds up the recognition by reducing the memory bandwidth requirement thereby the system is capable of performing real-time recognition for the DARPA resource management task which supports about 1000 words continuous speech recognition","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126405534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Estimation of Cell Loss Ratio and Cell Delay for ATM Networks using Novel Genetic Algorithm Approach 基于遗传算法的ATM网络丢包率和时延估计

2006 6th International Workshop on System on Chip for Real Time Applications Pub Date : 2006-12-01 DOI: 10.1109/IWSOC.2006.348267

H. El-Madbouly, M. Nassef

引用次数: 1

Better Area-Time Tradeoffs in an Expanded Design Space of Adder Architecture by Parameterizing Bit-width of Various Carry Propagated Sub-adder-blocks 通过参数化各种进位传播子加法器块的位宽，在扩展的加法器结构设计空间中实现更好的面积-时间权衡

2006 6th International Workshop on System on Chip for Real Time Applications Pub Date : 2006-12-01 DOI: 10.1109/IWSOC.2006.348255

Jeong-Gun Lee, Jeong-A Lee, Deok-Young Lee

引用次数: 4