Better Area-Time Tradeoffs in an Expanded Design Space of Adder Architecture by Parameterizing Bit-width of Various Carry Propagated Sub-adder-blocks

Abstract

Many adder designs exist for a designer to choose the fastest or the smallest or power efficient one. However, the performance of existing adders varies widely in their speed and area requirements, which in turn sometimes makes designers pay a high cost in area especially when the delay requirements exceeds the fastest speed of a specific adder, no matter how small the difference it is. To smooth such an increase in cost, we propose new adder architecture with expanded design space for better design tradeoffs. The new adder architecture, named a mutated adder architecture, restructures an adder with blocks of various carry propagated adders as sub-adder-components to aid a designer in selecting his/her adder with favorable characteristics. We formulate the problem of determining the bit-width of various carry propagate component adders in integer linear programming. We demonstrate the effectiveness of the new adder architecture using 128-bit adder design