Low Power Cache Architecture

Abstract

Power consumption is becoming a pressing issue in microprocessor design. Caches usually consume large part of the total power consumption of the chip. This paper introduces a novel low power cache architecture which is based on separating the in-coming cache data. Data is separated in two different banks: bank1 that mostly contains 1s data and bank0 that mostly contains 0s data. This separation in part reduces transistor switching activity inside the on-chip cache and hence dynamic power consumption. This papers shows up to 35% reduction for small sized cache of 1K and 9% for typical sized caches of 32K