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2006 6th International Workshop on System on Chip for Real Time Applications最新文献

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Dynamic Reconfiguration for Increased Functional Density 增加功能密度的动态重构
2006 6th International Workshop on System on Chip for Real Time Applications Pub Date : 2006-12-01 DOI: 10.1109/IWSOC.2006.348260
Nahla El-Araby, A. Wahba, H.S. Bedor
{"title":"Dynamic Reconfiguration for Increased Functional Density","authors":"Nahla El-Araby, A. Wahba, H.S. Bedor","doi":"10.1109/IWSOC.2006.348260","DOIUrl":"https://doi.org/10.1109/IWSOC.2006.348260","url":null,"abstract":"Using runtime reconfigurable systems can greatly increase the functional density of given area of silicon. Runtime reconfigurability is, for hardware designers, as virtual memory is, for software designers. By dynamically reconfiguring a device during its runtime, designers may implement so many functionalities on a limited area of silicon. This paper emphasizes this concept by implementing a set of digital filters. We chose the digital filters because of their importance to many computing tasks. It was shown that a considerable gain in the functional density is obtained when runtime reconfiguration is used","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131808602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Estimation of Cell Loss Ratio and Cell Delay for ATM Networks using Novel Genetic Algorithm Approach 基于遗传算法的ATM网络丢包率和时延估计
2006 6th International Workshop on System on Chip for Real Time Applications Pub Date : 2006-12-01 DOI: 10.1109/IWSOC.2006.348267
H. El-Madbouly, M. Nassef
{"title":"Estimation of Cell Loss Ratio and Cell Delay for ATM Networks using Novel Genetic Algorithm Approach","authors":"H. El-Madbouly, M. Nassef","doi":"10.1109/IWSOC.2006.348267","DOIUrl":"https://doi.org/10.1109/IWSOC.2006.348267","url":null,"abstract":"In this paper, an on line genetic algorithm (GA) is proposed for estimating the cell loss probability (CLP) and the cell delay in real time. They are key parameters to many vital functions in the network such as call admission (CAC), bandwidth allocation, etc. However, the CLR and delay depend usually on many unknown and unpredictable traffic parameters such as input traffic correlations. In this paper, a novel genetic algorithm to predict the CLR and delay in different sized systems based on both a small amount of information from these systems. This algorithm is used with real time traffic measurement to maintain and design the ATM network","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129662003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Instruction-Set Extension for Cryptographic Applications on Reconfigurable Platform 可重构平台上密码应用的指令集扩展
2006 6th International Workshop on System on Chip for Real Time Applications Pub Date : 2006-12-01 DOI: 10.1142/S0218126607004076
S. Majzoub, H. Diab
{"title":"Instruction-Set Extension for Cryptographic Applications on Reconfigurable Platform","authors":"S. Majzoub, H. Diab","doi":"10.1142/S0218126607004076","DOIUrl":"https://doi.org/10.1142/S0218126607004076","url":null,"abstract":"Recently, the area of reconfigurable computing has received considerable interest. Reconfigurable system is a specific name that is used for any machine that can be reconfigured during runtime to execute an algorithm as a hardware circuit. As a middle solution, reconfigurable systems stand halfway between traditional computing systems and specific hardware. This paper presents the mapping and performance analysis of two encryption algorithms, namely Rijndad and Twofish, on a coarse grain reconfigurable platform, namely MorphoSys. MorphoSys is a reconfigurable architecture targeted for multimedia applications. Since many cryptographic algorithms involve bitwise operations, bitwise instruction set extension was proposed to enhance the performance. The authors present the details of the mapping of the bitwise operations involved in the algorithms with thorough analysis. The methodology used can be utilized in other systems","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116235292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Delay Model for Networks-on-Chip Output-Queuing Router 片上网络输出排队路由器的延迟模型
2006 6th International Workshop on System on Chip for Real Time Applications Pub Date : 2006-12-01 DOI: 10.1109/IWSOC.2006.348272
H. Elmiligi, M. Watheq El-Kharashi, F. Gebali
{"title":"A Delay Model for Networks-on-Chip Output-Queuing Router","authors":"H. Elmiligi, M. Watheq El-Kharashi, F. Gebali","doi":"10.1109/IWSOC.2006.348272","DOIUrl":"https://doi.org/10.1109/IWSOC.2006.348272","url":null,"abstract":"Routers are vital modules in any networks-on-chip (NoC)-based design. To achieve an adequate performance, routers must be designed to match network inter-module traffic. One of the most important methods to accomplish this matching is to minimize the router delay. An early estimation of the router delay is critically needed to help designers specify the system timing constrains at higher levels of abstraction. In this paper, we present a delay model for NoC routers and explain how it can be used to study the effect of changing the queue size and the number of ports on the router delay and throughput. The novelty in our model is that it can be applied to techniques that use both clock edges to achieve low latency and, hence, improve the performance. The proposed model returns the router delay in terms of number of clock cycles as a technology-independent representation","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122769261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Automated Design Solutions for Fully Integrated Narrow-Band Low Noise Amplifiers 全集成窄带低噪声放大器的自动化设计解决方案
2006 6th International Workshop on System on Chip for Real Time Applications Pub Date : 2006-12-01 DOI: 10.1109/IWSOC.2006.348275
Y. Massoud, A. Nieuwoudt, T. Ragheb
{"title":"Automated Design Solutions for Fully Integrated Narrow-Band Low Noise Amplifiers","authors":"Y. Massoud, A. Nieuwoudt, T. Ragheb","doi":"10.1109/IWSOC.2006.348275","DOIUrl":"https://doi.org/10.1109/IWSOC.2006.348275","url":null,"abstract":"This paper presents accurate modeling and automated design solutions for narrow-band low noise amplifiers (LNA) in system-on-chip technology. An analytical circuit model was developed that captures the impact of integrated spiral inductor parasitics and transistor short channel effects. The LNA synthesis methodology leverages deterministic numerical nonlinear optimization techniques to simultaneously optimize both devices and passive components to yield integrated inductor values that are an order of magnitude less than those generated by traditional design techniques. When the optimized LNAs are simulated using Cadence SpectreRF, our methodology yields significant improvement in noise figure and gain over the values obtained using equation-based design techniques","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126113033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
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