Architectural Design and Implementation of an FPGA Softcore Based Speech Recognition System

2006 6th International Workshop on System on Chip for Real Time Applications Pub Date : 2006-12-01 DOI:10.1109/IWSOC.2006.348263

Kisun You, Hyun-Sub Lim, Wonyong Sung

{"title":"Architectural Design and Implementation of an FPGA Softcore Based Speech Recognition System","authors":"Kisun You, Hyun-Sub Lim, Wonyong Sung","doi":"10.1109/IWSOC.2006.348263","DOIUrl":null,"url":null,"abstract":"In spite of ever increasing logic capacity of FPGAs, the implementation of a large vocabulary speech recognition system encounters insufficient I/O bandwidth and internal memory capacity problems. In this paper, a speech recognition system architecture was described based on a softcore with hardware accelerators for the emission probability computation and the Viterbi beam search. The hardware accelerator for emission probability computation is equipped with the internal memory to effectively capture the access pattern of the acoustic model data which depend on the language model. The optimal memory configuration is determined by the proposed data partitioning strategy. The developed system has been implemented on a Xilinx Virtex-4 FPGA with MicroBlaze softcore processor along with various peripherals. The experimental results show that the proposed architecture speeds up the recognition by reducing the memory bandwidth requirement thereby the system is capable of performing real-time recognition for the DARPA resource management task which supports about 1000 words continuous speech recognition","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 6th International Workshop on System on Chip for Real Time Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWSOC.2006.348263","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 12

Abstract

In spite of ever increasing logic capacity of FPGAs, the implementation of a large vocabulary speech recognition system encounters insufficient I/O bandwidth and internal memory capacity problems. In this paper, a speech recognition system architecture was described based on a softcore with hardware accelerators for the emission probability computation and the Viterbi beam search. The hardware accelerator for emission probability computation is equipped with the internal memory to effectively capture the access pattern of the acoustic model data which depend on the language model. The optimal memory configuration is determined by the proposed data partitioning strategy. The developed system has been implemented on a Xilinx Virtex-4 FPGA with MicroBlaze softcore processor along with various peripherals. The experimental results show that the proposed architecture speeds up the recognition by reducing the memory bandwidth requirement thereby the system is capable of performing real-time recognition for the DARPA resource management task which supports about 1000 words continuous speech recognition

查看原文本刊更多论文

基于FPGA软核的语音识别系统体系结构设计与实现

尽管fpga的逻辑容量不断增加，但大词汇量语音识别系统的实现遇到了I/O带宽不足和内存容量不足的问题。本文描述了一种基于软核和硬件加速器的语音识别系统架构，用于发射概率计算和维特比波束搜索。发射概率计算硬件加速器内置存储器，有效捕获依赖于语言模型的声学模型数据的访问模式。最优内存配置由所提出的数据分区策略决定。所开发的系统已在Xilinx Virtex-4 FPGA上实现，该FPGA带有MicroBlaze软核处理器以及各种外围设备。实验结果表明，该体系结构降低了对内存带宽的要求，提高了识别速度，能够对DARPA资源管理任务进行实时识别，该任务支持约1000字的连续语音识别

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

2006 6th International Workshop on System on Chip for Real Time Applications

自引率

0.00%

发文量