Fragmentation Aware Placement in Reconfigurable Devices

Abstract

Partially reconfigurable field-programmable gate arrays (FPGAs) allow parts of the chip to be configured at runtime where each part could hold an independent task. Online placements of these tasks result in area fragmentation leading to a poor utilization of chip resources. In this paper, we propose a new metric for measuring area fragmentation. The new fragmentation metric gives an indication to the continuity of the occupied (or free) space and not the amount of occupied space. We show how this metric can be extended for multidimensional structures. We also show how this metric can be computed efficiently at run time. Next we use this measure during online placement of tasks on FPGAs, such that the chip fragmentation is reduced. Our results show improvement of chip utilization when using this fragmentation aware placement method over other placement methods with well known bottom left first fit, and best fit placement strategies