{"title":"蚀刻孔对微机电系统并联板可变电容器电容和调谐范围的影响","authors":"A. Elshurafa, E. El-Masry","doi":"10.1109/IWSOC.2006.348240","DOIUrl":null,"url":null,"abstract":"This paper presents extensive simulations of MEMS parallel plate variable capacitors with attention dedicated towards variations in etching holes' properties. For various separation distances between the plates, different hole sizes and density were created and capacitances were extracted. Within typical values, it was found that the configuration of the holes might affect the tuning range by no more than 16% at extreme cases of their theoretical counterparts. Simulations were done using finite element modeling","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"44 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":"{\"title\":\"Effects of Etching Holes on Capacitance and Tuning Range in MEMS Parallel Plate Variable Capacitors\",\"authors\":\"A. Elshurafa, E. El-Masry\",\"doi\":\"10.1109/IWSOC.2006.348240\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents extensive simulations of MEMS parallel plate variable capacitors with attention dedicated towards variations in etching holes' properties. For various separation distances between the plates, different hole sizes and density were created and capacitances were extracted. Within typical values, it was found that the configuration of the holes might affect the tuning range by no more than 16% at extreme cases of their theoretical counterparts. Simulations were done using finite element modeling\",\"PeriodicalId\":134742,\"journal\":{\"name\":\"2006 6th International Workshop on System on Chip for Real Time Applications\",\"volume\":\"44 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"15\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 6th International Workshop on System on Chip for Real Time Applications\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IWSOC.2006.348240\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 6th International Workshop on System on Chip for Real Time Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWSOC.2006.348240","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Effects of Etching Holes on Capacitance and Tuning Range in MEMS Parallel Plate Variable Capacitors
This paper presents extensive simulations of MEMS parallel plate variable capacitors with attention dedicated towards variations in etching holes' properties. For various separation distances between the plates, different hole sizes and density were created and capacitances were extracted. Within typical values, it was found that the configuration of the holes might affect the tuning range by no more than 16% at extreme cases of their theoretical counterparts. Simulations were done using finite element modeling
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
