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IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.最新文献

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Integration of Cu and extra low-k dielectric (k=2.5/spl sim/2.2) for 65/45/32nm generations 集成Cu和超低k介电(k=2.5/spl sim/2.2)，适用于65/45/32nm世代
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609273
Y. Su, J. Shieh, J.S. Tsai, C. Ting, C.H. Lin, C. Chou, J.W. Hsu, S. Jang, M. Liang
{"title":"Integration of Cu and extra low-k dielectric (k=2.5/spl sim/2.2) for 65/45/32nm generations","authors":"Y. Su, J. Shieh, J.S. Tsai, C. Ting, C.H. Lin, C. Chou, J.W. Hsu, S. Jang, M. Liang","doi":"10.1109/IEDM.2005.1609273","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609273","url":null,"abstract":"This paper investigated various approaches to integrate Cu and extra low-k dielectric (ELK, k=2.5~2.2) for dual damascene fabrication. We demonstrate a trench-first hard mask process flow without k degradation by ash-free process and a novel pore sealing technique. In addition, we have extended this pore sealing concept to a via-first PR mask approach for porous ELK of 2.2. Both optimized hard mask and PR mask process flows are demonstrated promising for Cu/ELK integration for 65/45/32nm generations","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"24 1","pages":"4 pp.-88"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80513401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Non-uniform degradation behavior across device width in RF power GaAs PHEMTs 射频功率GaAs phemt跨器件宽度的非均匀退化行为
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609471
A. Villanueva, J. D. del Alamo, T. Hisaka, K. Hayashi, M. Somerville
{"title":"Non-uniform degradation behavior across device width in RF power GaAs PHEMTs","authors":"A. Villanueva, J. D. del Alamo, T. Hisaka, K. Hayashi, M. Somerville","doi":"10.1109/IEDM.2005.1609471","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609471","url":null,"abstract":"We have studied the electrical degradation of RF power PHEMTs by means of light-emission measurements performed during bias-stress experiments. We show that electrical degradation can proceed in a highly non-uniform manner across the width of the device. We identify the origin of this as a small systematic non-uniformity in the recess geometry that impacts the electric field and the impact ionization rate on the drain of the device. Our research suggests that a close examination of the width distribution of electric field in RF power PHEMTs (and FETs in general) is essential to enhance their long-term reliability","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"12 1","pages":"783-786"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83563462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
The features and characteristics of 5M CMOS image sensor with 1.9/spl times/1.9/spl mu/m/sup 2/ pixels 1.9/spl倍/1.9/spl μ /m/sup 2/像素5M CMOS图像传感器的特点及特点
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609475
Changrok Moon, Jongwan Jung, Doowon Kwon, Seok-Ha Lee, J. Roh, Kee-Hyun Paik, Doo-Cheol Park, Hongki Kim, Heegeun Jeongc, J. Sim, Hyunpil Noh, Kangbok Lee, Duckhyung Lee, Kinam Kim
{"title":"The features and characteristics of 5M CMOS image sensor with 1.9/spl times/1.9/spl mu/m/sup 2/ pixels","authors":"Changrok Moon, Jongwan Jung, Doowon Kwon, Seok-Ha Lee, J. Roh, Kee-Hyun Paik, Doo-Cheol Park, Hongki Kim, Heegeun Jeongc, J. Sim, Hyunpil Noh, Kangbok Lee, Duckhyung Lee, Kinam Kim","doi":"10.1109/IEDM.2005.1609475","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609475","url":null,"abstract":"5 mega CMOS image sensor with 1.9mum-pitch pixels has been implemented with 0.13 mum low power CMOS process. By applying 4-shared pixel architecture, 2.5V operation voltage, and tight design rules for some critical layers in pixels, high fill factor and the corresponding high saturation could be obtained. Image lag was sufficiently suppressed by pulse-boosting of transfer gate voltage and electrical cross-talk was suppressed by use of n-type epitaxial layer. It is shown that several sophisticated processes improve sensitivity, temporal random noise, and dark current. With this technology, full 5-mega density CMOS image sensor chips have been successfully developed","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"33 1","pages":"4 pp.-798"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83620002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Local-damascene-finFET DRAM integration with p/sup +/ doped poly-silicon gate technology for sub-60nm device generations Local-damascene-finFET DRAM集成p/sup +/掺杂多晶硅栅极技术，用于sub-60nm器件世代
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609338
Yong-Sung Kim, Sang-Hyeon Lee, S. Shin, Sung-hee Han, Ju-Yong Lee, Jin-woo Lee, J. Han, Seung-Chul Yang, J. Sung, Eujime Lee, B. Song, Dong-jun Lee, D. Bae, Won-suk Yang, Yang-Keun Park, Kyuhyun Lee, B. Roh, Taeyoung Chung, Kinam Kim, Wonshik Lee
{"title":"Local-damascene-finFET DRAM integration with p/sup +/ doped poly-silicon gate technology for sub-60nm device generations","authors":"Yong-Sung Kim, Sang-Hyeon Lee, S. Shin, Sung-hee Han, Ju-Yong Lee, Jin-woo Lee, J. Han, Seung-Chul Yang, J. Sung, Eujime Lee, B. Song, Dong-jun Lee, D. Bae, Won-suk Yang, Yang-Keun Park, Kyuhyun Lee, B. Roh, Taeyoung Chung, Kinam Kim, Wonshik Lee","doi":"10.1109/IEDM.2005.1609338","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609338","url":null,"abstract":"We integrate FinFET DRAM in sub-60nm feature size. To avoid severe passing gate effects in FinFET cell array, we introduce a local damascene gate structure. Threshold voltage control of the ultra thin body transistors is successfully achieved by adopting p+ boron in-situ doped poly-silicon gate on the FinFET cells. As a result, very stable and uniform operation of FinFET cells is realized. The local damascene FinFET with p+ gate can become a highly feasible mainstream DRAM technology for sub-60nm low-power high-speed devices","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"21 1","pages":"315-318"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90238543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
BTI and charge trapping in germanium p- and n-MOSFETs with CVD HfO/sub 2/ gate dielectric CVD HfO/sub /栅极介质在锗p-和n- mosfet中的BTI和电荷捕获
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609406
N. Wu, Qingchun Zhang, Chunxiang Zhu, C. Shen, M. Li, D. Chan, N. Balasubramanian
{"title":"BTI and charge trapping in germanium p- and n-MOSFETs with CVD HfO/sub 2/ gate dielectric","authors":"N. Wu, Qingchun Zhang, Chunxiang Zhu, C. Shen, M. Li, D. Chan, N. Balasubramanian","doi":"10.1109/IEDM.2005.1609406","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609406","url":null,"abstract":"High performance Ge p- and n-MOSFETs with CVD HfO2 gate dielectric were fabricated. Charge trapping and Vth instability were investigated systematically for the first time for Ge MOSFET with different surface treatments (silicon passivation and surface nitridation) and compared to the Si devices. Our results show that: (1) Ge devices with silicon passivation yield better electrical performance and reliability than those with surface nitridation; (2) Ge transistors with silicon passivation exhibit less NBTI degradation than the silicon counterparts; probably due to the larger hole barrier in Ge/dielectric than in Si/dielectric; and (3) PBTI degradation of the Ge transistors is more severe than the silicon devices, which imposes an important reliability issue for Ge CMOS applications","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"4 1","pages":"4 pp.-558"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84784626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Mechanism of moisture uptake induced via failure and its impact on 45nm node interconnect design 失效诱导吸湿机理及其对45nm节点互连设计的影响
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609301
T. Fujimaki, K. Higashi, N. Nakamura, N. Matsunaga, K. Yoshida, N. Miyawaki, M. Hatano, M. Hasunuma, J. Wada, T. Nishioka, K. Akiyama, H. Kawashima, Y. Enomoto, T. Hasegawa, K. Honda, M. Iwai, S. Yamada, F. Matsuoka
{"title":"Mechanism of moisture uptake induced via failure and its impact on 45nm node interconnect design","authors":"T. Fujimaki, K. Higashi, N. Nakamura, N. Matsunaga, K. Yoshida, N. Miyawaki, M. Hatano, M. Hasunuma, J. Wada, T. Nishioka, K. Akiyama, H. Kawashima, Y. Enomoto, T. Hasegawa, K. Honda, M. Iwai, S. Yamada, F. Matsuoka","doi":"10.1109/IEDM.2005.1609301","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609301","url":null,"abstract":"Moisture induced via failure (MIVF) is studied for 45nm interconnect technology using porous low-k films. Test patterns are designed to examine the layout dependence of the MIVF. Some fundamental and important layout dependencies of the via resistance increase are investigated and considered for the first time. It has been found that the MIVF has not been suppressed, even though multiple vias structure is adopted. On the contrary, local wiring pattern density close to via and dummy wiring pattern area size strongly affect via resistance increase. A model with moisture ventilation can successfully explain those layout dependencies. It is confirmed that the MIVF is completely suppressed by the control of dummy pattern layout","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"29 1","pages":"183-186"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91128132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
High performance single grain si tfts inside a location-controlled grain by /spl mu/-czochralski process with capping layer 采用/spl mu/-czochralski工艺，在具有封盖层的位置控制颗粒内实现高性能单粒生长
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609509
R. Vikas, R. Ishihara, Y. Hiroshima, D. Abe, S. Inoue, T. Shimoda, J. Metselaar, C. Beenakker
{"title":"High performance single grain si tfts inside a location-controlled grain by /spl mu/-czochralski process with capping layer","authors":"R. Vikas, R. Ishihara, Y. Hiroshima, D. Abe, S. Inoue, T. Shimoda, J. Metselaar, C. Beenakker","doi":"10.1109/IEDM.2005.1609509","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609509","url":null,"abstract":"To enlarge the grain size of 2D location-controlled Si grain by mu-Czochralski process, capping layer (C/L) of SiO<sub>2</sub> in excimer-laser crystallization of amorphous Si thin film has been employed. With a 50 nm thick SiO<sub>2</sub> C/L on a 100 nm thick amorphous Si film, the diameter of the location-controlled grain was successfully increased up to 7.5 mum. Single-grain (SG) Si TFTs were fabricated inside a location-controlled grain with the SiO<sub>2</sub> C/L as a part of the gate oxide. Field effect mobility (mu<sub>FE</sub>) for electrons and holes of 510 cm<sup>2</sup>/Vs and of 210 cm<sup>2</sup>/Vs were obtained respectively","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"29 1","pages":"919-922"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76936628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
RFCPUs on glass and plastic substrates fabricated by TFT transfer technology 利用TFT转移技术制造玻璃和塑料基板上的rfcpu
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609284
H. Dembo, Y. Kurokawa, T. Ikeda, S. Iwata, K. Ohshima, J. Ishii, T. Tsurume, E. Sugiyama, D. Yamada, A. Isobe, S. Saito, K. Dairiki, N. Kusumoto, Y. Shionoiri, T. Atsumi, M. Fujita, H. Kobayashi, H. Takashina, Y. Yamashita, S. Yamazaki
{"title":"RFCPUs on glass and plastic substrates fabricated by TFT transfer technology","authors":"H. Dembo, Y. Kurokawa, T. Ikeda, S. Iwata, K. Ohshima, J. Ishii, T. Tsurume, E. Sugiyama, D. Yamada, A. Isobe, S. Saito, K. Dairiki, N. Kusumoto, Y. Shionoiri, T. Atsumi, M. Fujita, H. Kobayashi, H. Takashina, Y. Yamashita, S. Yamazaki","doi":"10.1109/IEDM.2005.1609284","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609284","url":null,"abstract":"On the basis of the fabrication of a CPU on glass as a digital circuit presented in B. Lee et al. (2003) and T. Ikeda et al. (2004), as well as the fabrication of a flexible CPU using a TFT transfer technology presented in T. Takayama et al. (2004), we have succeeded in the development of the world's first flexible RFCPUs (8bit, passive type) by adding to the CPU an antenna, an analog circuit, an encryption function and an RFID function, which operate using an RF signal with a frequency of 13.56MHz","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"70 1","pages":"125-127"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77389627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Mechanisms of hydrogen release in the breakdown of SiO/sub 2/-based gate oxides SiO/sub - 2基栅氧化物击穿过程中氢的释放机理
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609359
J. Suñé, E. Wu
{"title":"Mechanisms of hydrogen release in the breakdown of SiO/sub 2/-based gate oxides","authors":"J. Suñé, E. Wu","doi":"10.1109/IEDM.2005.1609359","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609359","url":null,"abstract":"The mechanisms of hydrogen release (HR) involved in the degradation and breakdown (BD) of SiO2-based gate dielectrics are studied by means of the analysis of charge to breakdown (QBD ) data versus electron energy, and comparing with scanning tunneling microscope (STM) experiments of H desorption from silicon surfaces. Our results reveal an important role of vibrational and electronic excitation mechanisms","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"4 1","pages":"388-391"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74040883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
Source/drain germanium condensation for p-channel strained ultra-thin body transistors p沟道应变超薄体晶体管的源/漏锗冷凝
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609389
K. Chui, K. Ang, A. Madan, Huiqi Wang, C. Tung, L. Wong, Yihua Wang, S. Choy, N. Balasubramanian, M. Li, G. Samudra, Y. Yeo
{"title":"Source/drain germanium condensation for p-channel strained ultra-thin body transistors","authors":"K. Chui, K. Ang, A. Madan, Huiqi Wang, C. Tung, L. Wong, Yihua Wang, S. Choy, N. Balasubramanian, M. Li, G. Samudra, Y. Yeo","doi":"10.1109/IEDM.2005.1609389","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609389","url":null,"abstract":"This paper reports a novel technique to fabricate uniaxial compressive strained p-channel transistors with silicon-germanium (SiGe) source and drain (S/D) stressors. The process involves local Ge condensation of a selectively grown SiGe region, thus driving Ge into and enriching the Ge concentration in the source and drain regions adjacent to the transistor channel. The process is particularly suitable for ultra-thin-body (UTB) transistors since it eliminates the need for a Si recess etch prior to SiGe epitaxy. In addition, the required thermal budget for Ge condensation is not prohibitive for UTB structures. High Ge mole fraction could be achieved in the S/D regions, leading to higher strain levels in the transistor channel. We demonstrate the feasibility of this technique in silicon-on-insulator (SOI) P-MOSFETs with a gate length LG of 90 nm. Drive current IDsat enhancement of up to 35% was observed","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"219 1","pages":"493-496"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75689596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
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