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IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.最新文献

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CMOS and interconnect reliability gate dielectric breakdown - modeling and mechanism CMOS与互连可靠性栅极介电击穿的建模与机理
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609358
P. Nicollian, K. Eriguchi
{"title":"CMOS and interconnect reliability gate dielectric breakdown - modeling and mechanism","authors":"P. Nicollian, K. Eriguchi","doi":"10.1109/IEDM.2005.1609358","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609358","url":null,"abstract":"","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"8 1","pages":"387-387"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87099897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A new logic family based on hybrid MOSFET-polysilicon nanowires 基于混合mosfet -多晶硅纳米线的新型逻辑系列
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609325
S. Ecoffey, M. Mazza, V. Pott, D. Bouvet, A. Schmid, Y. Leblebici, M.J. Declereq, A. Ionescu
{"title":"A new logic family based on hybrid MOSFET-polysilicon nanowires","authors":"S. Ecoffey, M. Mazza, V. Pott, D. Bouvet, A. Schmid, Y. Leblebici, M.J. Declereq, A. Ionescu","doi":"10.1109/IEDM.2005.1609325","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609325","url":null,"abstract":"A new logic family based on ultra-thin film (10nm) nanograins (5 to 20nm) polysilicon wires (polySiNW) is proposed, validated and studied. This logic family can be operated from 4K up to 400K and hybridized with conventional CMOS. Ultra low power dissipation in the order of hundreds of pWs has been observed, which is outperforming CMOS technology, in terms of power consumption, by orders of magnitude","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"3 1","pages":"269-272"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87197236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
PECVD-oxynitride gas chromatographic columns pecvd -氮化氧气相色谱柱
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609334
M. Agah, K. Wise
{"title":"PECVD-oxynitride gas chromatographic columns","authors":"M. Agah, K. Wise","doi":"10.1109/IEDM.2005.1609334","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609334","url":null,"abstract":"This paper describes the realization of low-power high-speed micro gas chromatography columns for portable gas analysis systems. The 25cm-long ultra-low-mass MEMS columns, fabricated using stress-free PECVD-oxynitride films in a CMOS-compatible process, allow high-performance separations of n-alkane gas mixtures, are capable of multi-second analysis, and can dissipate less than 10mW at 150degC in vacuum","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"2 1","pages":"4 pp.-305"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90080534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
AlGaN/GaN devices for future power switching systems 用于未来电源开关系统的AlGaN/GaN器件
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609355
D. Ueda, T. Murata, M. Hikita, S. Nakazawa, M. Kuroda, H. Ishida, M. Yanagihara, K. Inoue, T. Ueda, Y. Uemoto, T. Tanaka, T. Egawa
{"title":"AlGaN/GaN devices for future power switching systems","authors":"D. Ueda, T. Murata, M. Hikita, S. Nakazawa, M. Kuroda, H. Ishida, M. Yanagihara, K. Inoue, T. Ueda, Y. Uemoto, T. Tanaka, T. Egawa","doi":"10.1109/IEDM.2005.1609355","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609355","url":null,"abstract":"GaN/AlGaN device technologies are presented aiming at the applications to power switching systems. In order to reduce on-resistance (Ron), we developed SL (super lattice) capping and QA (quaternary alloy) over-layer techniques for GaN/AlGaN HFET. Further, we achieved almost the same mobility keeping the same 2DEG density for GaN/AlGaN hetero structure grown on Si (111) substrates, which will make the cost comparable to conventional Si one. The experimentally obtained RonA of the FET is 1.9 mOmegacm2, which is 14 times lower than that of Si ones. Additionally, a novel approach to realize enhancement-mode operation of GaN/AlGaN FET is examined over R-plane sapphire, where non-polar AlGaN/GaN heterostructure, free from polarization charge, can be grown","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"34 1","pages":"377-380"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85570428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Mechanisms of hydrogen release in the breakdown of SiO/sub 2/-based gate oxides SiO/sub - 2基栅氧化物击穿过程中氢的释放机理
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609359
J. Suñé, E. Wu
{"title":"Mechanisms of hydrogen release in the breakdown of SiO/sub 2/-based gate oxides","authors":"J. Suñé, E. Wu","doi":"10.1109/IEDM.2005.1609359","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609359","url":null,"abstract":"The mechanisms of hydrogen release (HR) involved in the degradation and breakdown (BD) of SiO2-based gate dielectrics are studied by means of the analysis of charge to breakdown (QBD ) data versus electron energy, and comparing with scanning tunneling microscope (STM) experiments of H desorption from silicon surfaces. Our results reveal an important role of vibrational and electronic excitation mechanisms","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"4 1","pages":"388-391"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74040883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
Practical finFET design considering GIDL for LSTP (low standby power) devices 考虑GIDL的LSTP(低待机功率)器件的实用finFET设计
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609526
K. Tanaka, K. Takeuchi, M. Hane
{"title":"Practical finFET design considering GIDL for LSTP (low standby power) devices","authors":"K. Tanaka, K. Takeuchi, M. Hane","doi":"10.1109/IEDM.2005.1609526","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609526","url":null,"abstract":"Practical design of double-gate undoped-channel FinFET has been investigated through 3D device simulations considering gate-induced drain leakage (GIDL). Optimization of FinFET structure was carried out for hp45 low standby power (LSTP) device (Lg = 25nm). GIDL is reduced by using gradual and offset source/drain (S/D) profile while degradation of drive current is minimized. Through the optimization of lateral spread and offset of S/D profile, the ITRS specifications for drive current and off-state leakage current are achievable by FinFET with 10nm fin width","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"40 1","pages":"980-983"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73491242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
RFCPUs on glass and plastic substrates fabricated by TFT transfer technology 利用TFT转移技术制造玻璃和塑料基板上的rfcpu
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609284
H. Dembo, Y. Kurokawa, T. Ikeda, S. Iwata, K. Ohshima, J. Ishii, T. Tsurume, E. Sugiyama, D. Yamada, A. Isobe, S. Saito, K. Dairiki, N. Kusumoto, Y. Shionoiri, T. Atsumi, M. Fujita, H. Kobayashi, H. Takashina, Y. Yamashita, S. Yamazaki
{"title":"RFCPUs on glass and plastic substrates fabricated by TFT transfer technology","authors":"H. Dembo, Y. Kurokawa, T. Ikeda, S. Iwata, K. Ohshima, J. Ishii, T. Tsurume, E. Sugiyama, D. Yamada, A. Isobe, S. Saito, K. Dairiki, N. Kusumoto, Y. Shionoiri, T. Atsumi, M. Fujita, H. Kobayashi, H. Takashina, Y. Yamashita, S. Yamazaki","doi":"10.1109/IEDM.2005.1609284","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609284","url":null,"abstract":"On the basis of the fabrication of a CPU on glass as a digital circuit presented in B. Lee et al. (2003) and T. Ikeda et al. (2004), as well as the fabrication of a flexible CPU using a TFT transfer technology presented in T. Takayama et al. (2004), we have succeeded in the development of the world's first flexible RFCPUs (8bit, passive type) by adding to the CPU an antenna, an analog circuit, an encryption function and an RFID function, which operate using an RF signal with a frequency of 13.56MHz","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"70 1","pages":"125-127"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77389627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
High performance single grain si tfts inside a location-controlled grain by /spl mu/-czochralski process with capping layer 采用/spl mu/-czochralski工艺，在具有封盖层的位置控制颗粒内实现高性能单粒生长
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609509
R. Vikas, R. Ishihara, Y. Hiroshima, D. Abe, S. Inoue, T. Shimoda, J. Metselaar, C. Beenakker
{"title":"High performance single grain si tfts inside a location-controlled grain by /spl mu/-czochralski process with capping layer","authors":"R. Vikas, R. Ishihara, Y. Hiroshima, D. Abe, S. Inoue, T. Shimoda, J. Metselaar, C. Beenakker","doi":"10.1109/IEDM.2005.1609509","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609509","url":null,"abstract":"To enlarge the grain size of 2D location-controlled Si grain by mu-Czochralski process, capping layer (C/L) of SiO<sub>2</sub> in excimer-laser crystallization of amorphous Si thin film has been employed. With a 50 nm thick SiO<sub>2</sub> C/L on a 100 nm thick amorphous Si film, the diameter of the location-controlled grain was successfully increased up to 7.5 mum. Single-grain (SG) Si TFTs were fabricated inside a location-controlled grain with the SiO<sub>2</sub> C/L as a part of the gate oxide. Field effect mobility (mu<sub>FE</sub>) for electrons and holes of 510 cm<sup>2</sup>/Vs and of 210 cm<sup>2</sup>/Vs were obtained respectively","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"29 1","pages":"919-922"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76936628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Source/drain germanium condensation for p-channel strained ultra-thin body transistors p沟道应变超薄体晶体管的源/漏锗冷凝
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609389
K. Chui, K. Ang, A. Madan, Huiqi Wang, C. Tung, L. Wong, Yihua Wang, S. Choy, N. Balasubramanian, M. Li, G. Samudra, Y. Yeo
{"title":"Source/drain germanium condensation for p-channel strained ultra-thin body transistors","authors":"K. Chui, K. Ang, A. Madan, Huiqi Wang, C. Tung, L. Wong, Yihua Wang, S. Choy, N. Balasubramanian, M. Li, G. Samudra, Y. Yeo","doi":"10.1109/IEDM.2005.1609389","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609389","url":null,"abstract":"This paper reports a novel technique to fabricate uniaxial compressive strained p-channel transistors with silicon-germanium (SiGe) source and drain (S/D) stressors. The process involves local Ge condensation of a selectively grown SiGe region, thus driving Ge into and enriching the Ge concentration in the source and drain regions adjacent to the transistor channel. The process is particularly suitable for ultra-thin-body (UTB) transistors since it eliminates the need for a Si recess etch prior to SiGe epitaxy. In addition, the required thermal budget for Ge condensation is not prohibitive for UTB structures. High Ge mole fraction could be achieved in the S/D regions, leading to higher strain levels in the transistor channel. We demonstrate the feasibility of this technique in silicon-on-insulator (SOI) P-MOSFETs with a gate length LG of 90 nm. Drive current IDsat enhancement of up to 35% was observed","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"219 1","pages":"493-496"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75689596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Carbon nanotube interconnects: implications for performance, power dissipation and thermal management 碳纳米管互连:对性能、功耗和热管理的影响
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609320
N. Srivastava, R. Joshi, K. Banerjee
{"title":"Carbon nanotube interconnects: implications for performance, power dissipation and thermal management","authors":"N. Srivastava, R. Joshi, K. Banerjee","doi":"10.1109/IEDM.2005.1609320","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609320","url":null,"abstract":"This paper presents a comprehensive evaluation of carbon nanotube bundle interconnects from all aspects critical to VLSI circuits - performance, power dissipation and reliability - while taking into account practical limitations of the technology. A novel delay model for CNT bundle interconnects has been developed, using which it is shown that CNT bundles can significantly improve the performance of long global interconnects with minimal additional power dissipation (for maximum metallic CNT density). While it is well known that CNT bundle interconnects can carry much higher current densities than copper, their impact on back-end thermal management and interconnect temperature rise is presented here for the first time. It is shown that the use of CNT bundle vias integrated with copper interconnects can improve copper interconnect lifetime by two orders of magnitude and also reduce optimal global interconnect delay by as much as 30%","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"9 1","pages":"249-252"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80074334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 87
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