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[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs最新文献

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A novel trench planarization technique using polysilicon refill, polysilicon oxidation, and oxide etchback 一种利用多晶硅填充、多晶硅氧化和氧化物腐蚀的新型沟槽平面化技术
[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 1991-04-22 DOI: 10.1109/ISPSD.1991.146098
K. Shenai, W. Hennessy, M. Ghezzo
{"title":"A novel trench planarization technique using polysilicon refill, polysilicon oxidation, and oxide etchback","authors":"K. Shenai, W. Hennessy, M. Ghezzo","doi":"10.1109/ISPSD.1991.146098","DOIUrl":"https://doi.org/10.1109/ISPSD.1991.146098","url":null,"abstract":"Summary form only given. A trench planarization technique is reported which uses polysilicon refill and sequential polysilicon oxidation and oxide etchback processes. Silicon trenches with varying trench depths (1-10 mu m) and trench aspect ratios were successfully planarized using this technique. The process uniformity across 4 in. dia. silicon wafers was excellent with MOS gate yields in excess of 95%. Trench capacitors were fabricated and tested for MOS gate interface characteristics and reliability. Trench power MOSFETs were fabricated using a conventional two-step RIE (reactive ion etching) process as well as the proposed technique. It was found that the proposed technique resulted in significant improvements in gate yield and process uniformity, and is easily adaptable in a manufacturing environment for fabricating high-density trench-based active devices, isolation structures, and interconnections.<<ETX>>","PeriodicalId":127986,"journal":{"name":"[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124815342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Extension of RESURF principle to dielectrically isolated power devices 将RESURF原理扩展到介质隔离的电力设备
[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 1991-04-22 DOI: 10.1109/ISPSD.1991.146059
Y. Huang, B. J. Baliga
{"title":"Extension of RESURF principle to dielectrically isolated power devices","authors":"Y. Huang, B. J. Baliga","doi":"10.1109/ISPSD.1991.146059","DOIUrl":"https://doi.org/10.1109/ISPSD.1991.146059","url":null,"abstract":"The RESURF (reduced surface field) principle has been extended to dielectrically isolated power devices including the effect of the formation of an inversion layer under the isolating oxide. Two device structures that allow high voltage operation have been investigated. Extensive two-dimensional simulations have been performed to relate the breakdown voltage to the doping and length of the drift region, and the thicknesses of the silicon layer and isolating oxide. It has been shown that lateral devices with breakdown voltages up to 600 V can be obtained.<<ETX>>","PeriodicalId":127986,"journal":{"name":"[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132167273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 105
Improvement of high speed blocking voltage by means of metal field plate for GaAs Schottky power rectifiers 用金属场板改进GaAs肖特基功率整流器的高速阻断电压
[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 1991-04-22 DOI: 10.1109/ISPSD.1991.146089
K. Ohtsuka, Y. Usui
{"title":"Improvement of high speed blocking voltage by means of metal field plate for GaAs Schottky power rectifiers","authors":"K. Ohtsuka, Y. Usui","doi":"10.1109/ISPSD.1991.146089","DOIUrl":"https://doi.org/10.1109/ISPSD.1991.146089","url":null,"abstract":"In GaAs power SBDs (Schottky barrier diodes) with a RESP (resistive Schottky barrier field plate) structure, a blocking voltage was observed when a reverse voltage was rapidly applied to GaAs SBDs. This voltage was termed high speed blocking voltage. Experiments indicated that the high speed blocking voltage was lower than the static blocking voltage. To improve the high speed blocking voltage without decreasing static voltage, the reverse characteristics of several structures of GaAs SBDs were investigated through experiments, and the high speed blocking voltage was successfully simulated using SPICE. The combination of a metal field plate structure and a RESP structure resulted in a high speed blocking voltage as high as the static blocking voltage for GaAs power SBDs.<<ETX>>","PeriodicalId":127986,"journal":{"name":"[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134343663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
High voltage video amplifier IC for color television 彩色电视用高压视频放大IC
[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 1991-04-22 DOI: 10.1109/ISPSD.1991.146107
K. Kawamoto, T. Tanaka, S. Sugayama, H. Ohki, S. Terada, M. Kamiya
{"title":"High voltage video amplifier IC for color television","authors":"K. Kawamoto, T. Tanaka, S. Sugayama, H. Ohki, S. Terada, M. Kamiya","doi":"10.1109/ISPSD.1991.146107","DOIUrl":"https://doi.org/10.1109/ISPSD.1991.146107","url":null,"abstract":"A high-voltage video amplifier IC with an automatic white balance circuit has been developed for color television (CTV). The IC can automatically adjust the white balance of the CTV by detecting the CRT (cathode ray tube) cathode currents. This enables the TV production line to eliminate the adjustment process. The frequency response of the video signal amplifier is as high as 10 MHz, so that the IC meets the requirements for larger TV screens and higher resolution.<<ETX>>","PeriodicalId":127986,"journal":{"name":"[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116118743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Packaging technology for smart power applications 智能电源应用的封装技术
[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 1991-04-22 DOI: 10.1109/ISPSD.1991.146057
C. Neugebauer
{"title":"Packaging technology for smart power applications","authors":"C. Neugebauer","doi":"10.1109/ISPSD.1991.146057","DOIUrl":"https://doi.org/10.1109/ISPSD.1991.146057","url":null,"abstract":"The author briefly reviews packaging technology for smart power applications. Attention is given to packaging for low to medium voltages and for high voltages; to protective networks; and to smart power hybrids.<<ETX>>","PeriodicalId":127986,"journal":{"name":"[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121925145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Impact of dielectric isolation technology on power ICs 介电隔离技术对功率集成电路的影响
[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 1991-04-22 DOI: 10.1109/ISPSD.1991.146056
A. Nakagawa
{"title":"Impact of dielectric isolation technology on power ICs","authors":"A. Nakagawa","doi":"10.1109/ISPSD.1991.146056","DOIUrl":"https://doi.org/10.1109/ISPSD.1991.146056","url":null,"abstract":"The impact and advantages of dielectric isolation (DI) are discussed, and the directions of DI research are highlighted. It is noted that DI is a superior method for integrating many kinds of devices in a single chip. The success of a high voltage telecommunication IC, called SLIC, has advanced the technology of DI. It is suggested that the next driving force will be high voltage and relatively large current power ICs, integrating a small power system unit into a single chip. This small-scale version of system-on-chip ICs will fully utilize the advantages of the DI method, operated at a high temperature when installed inside such instruments as motors or lamps. This will realize simplified and small sized power systems or equipment. Research efforts for a low cost DI method will be led by SOI (silicon on insulator) technology using several-micron-thick-or-less silicon layers. This will simplify the device isolation and even attain high voltages.<<ETX>>","PeriodicalId":127986,"journal":{"name":"[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs","volume":"706 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127965706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
SIPOS-passivation for high voltage power devices with planar junction termination 平面结端高压功率器件的sipos钝化
[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 1991-04-22 DOI: 10.1109/ISPSD.1991.146086
T. Stockmeier, K. Lilja
{"title":"SIPOS-passivation for high voltage power devices with planar junction termination","authors":"T. Stockmeier, K. Lilja","doi":"10.1109/ISPSD.1991.146086","DOIUrl":"https://doi.org/10.1109/ISPSD.1991.146086","url":null,"abstract":"Power diodes have been fabricated with a planar junction termination suitable for breakdown voltages up to 6.2 kV. The devices were passivated with a double layer of SIPOS (semi-insulating polycrystalline silicon) and silicon nitride, directly deposited on the silicon surface. The influence of the SIPOS layer on the current distribution in the device while in the blocking state was investigated by numerical simulation and experimentally. It was found that SIPOS acts simply as a resistive layer and that the portion of the reverse current which flows through the passivation layer is given by the balance of the resistances of the space charge region and the SIPOS layer. Therefore, if the resistance of the SIPOS layer is adjusted carefully (by its oxygen content and its lateral and vertical dimensions), high voltage diodes can be passivated with a semi-insulating material, and an excellent blocking behavior can be achieved.<<ETX>>","PeriodicalId":127986,"journal":{"name":"[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115262505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Operation of IGBTs at low temperatures 低温下igbt的运行
[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 1991-04-22 DOI: 10.1109/ISPSD.1991.146105
T. Chow, K. So, D. Lau
{"title":"Operation of IGBTs at low temperatures","authors":"T. Chow, K. So, D. Lau","doi":"10.1109/ISPSD.1991.146105","DOIUrl":"https://doi.org/10.1109/ISPSD.1991.146105","url":null,"abstract":"The static and dynamic performance of 600 V, n- and p-channel, vertical insulated-gate bipolar transistors (IGBTs) at temperatures as low as 77 K has been measured and analyzed. Both types of IGBTs demonstrate a better performance at low temperatures in turn-off times and maximum gate controllable current, at the expense of a slightly higher forward drop.<<ETX>>","PeriodicalId":127986,"journal":{"name":"[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128762780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A new device model of VDMOSFET for SPICE simulations 一种用于SPICE仿真的VDMOSFET器件模型
[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 1991-04-22 DOI: 10.1109/ISPSD.1991.146073
N. Dogan, E. Lozano
{"title":"A new device model of VDMOSFET for SPICE simulations","authors":"N. Dogan, E. Lozano","doi":"10.1109/ISPSD.1991.146073","DOIUrl":"https://doi.org/10.1109/ISPSD.1991.146073","url":null,"abstract":"The authors present a novel SPICE model for VDMOSFET which is based on analytical expressions for I-V and C-V characteristics of the device. The device model parameters were extracted from measured I-V and C-V characteristics of Siliconix VNDU 12 and DC52 VDMOSFETs. The model has been incorporated in the source code of SPICE3C1 which runs on IBM PC or compatible. Simulations using this model agree well with experimental data for both DC and transient responses. The model can be used in the simulation and design of switching power supplies and other circuits which use power MOSFETs.<<ETX>>","PeriodicalId":127986,"journal":{"name":"[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126814277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A scaled CMOS-compatible smart power IC technology 一种可兼容cmos的智能电源集成电路技术
[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 1991-04-22 DOI: 10.1109/ISPSD.1991.146065
S. Wong, M.J. Kim, J. C. Young, S. Mukherjee
{"title":"A scaled CMOS-compatible smart power IC technology","authors":"S. Wong, M.J. Kim, J. C. Young, S. Mukherjee","doi":"10.1109/ISPSD.1991.146065","DOIUrl":"https://doi.org/10.1109/ISPSD.1991.146065","url":null,"abstract":"An integrated VDMOS-based PIC process was developed to increase the cost effectiveness and performance of 60 V high current circuits. Compact 60 V CMOS elements and a 140 m Omega -mm/sup 2/ VDMOS were integrated into a 3 mu m CMOS process using only one additional mask. This increased level of integration allowed the use of a cell-based ASPIC (application-specific power IC) methodology as an attractive alternative to conventional full-custom approaches. This was demonstrated in the development of a 10 A intelligent power switch for automotive applications.<<ETX>>","PeriodicalId":127986,"journal":{"name":"[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131636680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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