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[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs最新文献

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The base resistance controlled thyristor (BRT)-a new MOS gated power thyristor 基极电阻控制晶闸管(BRT)是一种新型MOS门控功率晶闸管
[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 1991-04-22 DOI: 10.1109/ISPSD.1991.146084
M. Nandakumar, B. J. Baliga, M. S. Shekar, S. Tandon, A. Reisman
{"title":"The base resistance controlled thyristor (BRT)-a new MOS gated power thyristor","authors":"M. Nandakumar, B. J. Baliga, M. S. Shekar, S. Tandon, A. Reisman","doi":"10.1109/ISPSD.1991.146084","DOIUrl":"https://doi.org/10.1109/ISPSD.1991.146084","url":null,"abstract":"A novel MOS gated thyristor structure called the base resistance controlled thyristor is proposed. In this device structure, turn off of a thyristor built with a N drift region is achieved by diverting hole current from its p-base to an adjacent p/sup +/ region through a p-channel MOSFET. This has the effect of reducing the p-base resistance and raising the holding current of the thyristor above the operating current level. The device concept has been verified by two-dimensional numerical simulations. Experimental results on 600 V devices fabricated with an IGBT process corroborate theoretical predictions.<<ETX>>","PeriodicalId":127986,"journal":{"name":"[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs","volume":"415 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124814989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
A novel high voltage three-phase monolithic inverter IC with two current levels sensing 一种新型的双电平感应高压三相单片逆变电路
[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 1991-04-22 DOI: 10.1109/ISPSD.1991.146110
H. Miyazaki, N. Sakurai, K. Onda, T. Tanaka, M. Mori, M. Wada, H. Matsuzaki
{"title":"A novel high voltage three-phase monolithic inverter IC with two current levels sensing","authors":"H. Miyazaki, N. Sakurai, K. Onda, T. Tanaka, M. Mori, M. Wada, H. Matsuzaki","doi":"10.1109/ISPSD.1991.146110","DOIUrl":"https://doi.org/10.1109/ISPSD.1991.146110","url":null,"abstract":"A 250-V 1-A three-phase monolithic inverter IC (ECN3010) for variable-speed motor drives has been fabricated. Six insulated-gate bipolar transistors (IGBTs) and fast recovery diodes are integrated on one chip, for the output stages, using dielectric isolation. The IC provides many functions for driving a DC brushless motor by itself. A two-current-level sensing circuit has been developed to limit the motor start-up current and to turn off all the IGBTs when a short-circuit load occurs. The accuracy of the sensing circuit and its temperature dependence are discussed.<<ETX>>","PeriodicalId":127986,"journal":{"name":"[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128225377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Computer aided design tools for power IC's 电源集成电路的计算机辅助设计工具
[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 1991-04-22 DOI: 10.1109/ISPSD.1991.146055
W. Fichtner, J. Burgler, H. Dettmer, H. Lendenmann, S. Muller, M. Westermann
{"title":"Computer aided design tools for power IC's","authors":"W. Fichtner, J. Burgler, H. Dettmer, H. Lendenmann, S. Muller, M. Westermann","doi":"10.1109/ISPSD.1991.146055","DOIUrl":"https://doi.org/10.1109/ISPSD.1991.146055","url":null,"abstract":"The authors give an overview of the status of CAD (computer-aided design) tools in power IC design, especially the use of simulation tools and computer-aided layout techniques. They illustrate the possibilities of these tools with two examples from a recent MOS controlled thyristor (MCT) design effort.<<ETX>>","PeriodicalId":127986,"journal":{"name":"[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127074500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
High voltage silicon-on-insulator (SOI) MOSFETs 高压绝缘体上硅(SOI) mosfet
[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 1991-04-22 DOI: 10.1109/ISPSD.1991.146061
Q. Lu, P. Ratnam, C. Salama
{"title":"High voltage silicon-on-insulator (SOI) MOSFETs","authors":"Q. Lu, P. Ratnam, C. Salama","doi":"10.1109/ISPSD.1991.146061","DOIUrl":"https://doi.org/10.1109/ISPSD.1991.146061","url":null,"abstract":"Novel lateral high-voltage SOI MOSFETs capable of withstanding up to 400 V are presented. The design optimization, fabrication, and experimental results obtained for these devices are presented. The devices can be implemented using a CMOS-SOI compatible process. To ensure high voltage capability, the reduced surface field (RESURF) technique and field plates are used. The blocking, DC, and transient characteristics of the devices were investigated both theoretically and experimentally. Optimization of the process parameters involved in the design of the structures is presented.<<ETX>>","PeriodicalId":127986,"journal":{"name":"[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs","volume":"101 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120977467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Partial lifetime control in IGBT by helium irradiation through mask patterns 通过掩膜模式的氦辐照控制IGBT的部分寿命
[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 1991-04-22 DOI: 10.1109/ISPSD.1991.146095
H. Akiyama, M. Harada, H. Kondoh, Y. Akasaka
{"title":"Partial lifetime control in IGBT by helium irradiation through mask patterns","authors":"H. Akiyama, M. Harada, H. Kondoh, Y. Akasaka","doi":"10.1109/ISPSD.1991.146095","DOIUrl":"https://doi.org/10.1109/ISPSD.1991.146095","url":null,"abstract":"Partial lifetime control for IGBTs (insulated-gate bipolar transistors) performed by irradiated helium ions through a stainless steel mask is studied. This control technique localizes the presence of carrier recombination centers in the lateral direction as well as in depth profile. Using this technique, one can obtain better trade-off curves between on-state voltage and turn-off loss compared with maskless irradiation. Turn-off loss is reduced to 41% of that in the case of maskless irradiation at the same on-state voltage.<<ETX>>","PeriodicalId":127986,"journal":{"name":"[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123064144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Low on-resistance power LDMOSFET using double metal process technology 低导通功率LDMOSFET采用双金属工艺技术
[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 1991-04-22 DOI: 10.1109/ISPSD.1991.146067
M. Hoshi, T. Mihara, T. Matsushita, Y. Hirota
{"title":"Low on-resistance power LDMOSFET using double metal process technology","authors":"M. Hoshi, T. Mihara, T. Matsushita, Y. Hirota","doi":"10.1109/ISPSD.1991.146067","DOIUrl":"https://doi.org/10.1109/ISPSD.1991.146067","url":null,"abstract":"A low on-resistance lateral power FET which is suitable for the H-bridge motorcontrol IPD (intelligent power device) for automatic applications is described. The LDMOSFET was fabricated using the double metal process technology with a hexagonal pattern layout which increases the cell density. The device with cell density as high as 5.1 million cells/in/sup 2/ has a specific on-resistance of 1.15 m Omega -cm/sup 2/ under pulsed drain bias conditions, and the reverse blocking voltage is 42 V. This on-resistance represents the lowest among the lateral type power FETs with similar blocking voltage.<<ETX>>","PeriodicalId":127986,"journal":{"name":"[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131544791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
SPT-a new smart power technology with a fully self aligned DMOS cell spt -一种新的智能电源技术，具有完全自对准的DMOS电池
[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 1991-04-22 DOI: 10.1109/ISPSD.1991.146097
A. Preussger, E. Glenz, K. Heift, K. Malek, W. Schwetlick, K. Wiesinger, W. M. Werner
{"title":"SPT-a new smart power technology with a fully self aligned DMOS cell","authors":"A. Preussger, E. Glenz, K. Heift, K. Malek, W. Schwetlick, K. Wiesinger, W. M. Werner","doi":"10.1109/ISPSD.1991.146097","DOIUrl":"https://doi.org/10.1109/ISPSD.1991.146097","url":null,"abstract":"Describes a novel smart power technology (SPT) which integrates n-channel (DMOS) power transistors for multichannel applications, p-channel high voltage transistors, and CMOS logic and bipolar devices. The DMOS was optimized with respect to minimal R/sub on/ (on-resistance) and breakdown voltage greater than 75 V. With a self-aligned DMOS contact cell a specific R/sub on/ of 0.28 Omega -mm/sup 2/ without metal contribution was reached.<<ETX>>","PeriodicalId":127986,"journal":{"name":"[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs","volume":"311 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133115590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A novel soft and fast recovery diode (SFD) with thin p-layer formed by Al-Si electrode 一种新型的铝硅电极薄p层软快速恢复二极管(SFD)
[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 1991-04-22 DOI: 10.1109/ISPSD.1991.146079
M. Mori, Y. Yasuda, N. Sakurai, Y. Sugawara
{"title":"A novel soft and fast recovery diode (SFD) with thin p-layer formed by Al-Si electrode","authors":"M. Mori, Y. Yasuda, N. Sakurai, Y. Sugawara","doi":"10.1109/ISPSD.1991.146079","DOIUrl":"https://doi.org/10.1109/ISPSD.1991.146079","url":null,"abstract":"A novel, soft and fast recovery diode (SFD) is presented which has extremely thin p-layers formed by an Al-Si electrode and deep p/sup +/-layers. By using the thin p-layer, the hole density in the n/sup -/-layer close to the p-n junction is reduced, and a 1/2.5 lower recovery current peak, 1/3 lower recovery current change, and 1.5 times faster recovery time are realized compared to a conventional p-n diode. Moreover, increasing the barrier height of the p-layer causes the leakage current and forward voltage drop to decrease. It is also demonstrated that electrical noise and turn-on loss of an IGBT module in an inverter circuit can be significantly improved by using the SFD as a free wheeling diode.<<ETX>>","PeriodicalId":127986,"journal":{"name":"[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115970505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 37
Experimental demonstration of the emitter switched thyristor 发射极开关晶闸管的实验演示
[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 1991-04-22 DOI: 10.1109/ISPSD.1991.146082
M. S. Shekar, B. J. Baliga, M. Nandakumar, S. Tandon, A. Reisman
{"title":"Experimental demonstration of the emitter switched thyristor","authors":"M. S. Shekar, B. J. Baliga, M. Nandakumar, S. Tandon, A. Reisman","doi":"10.1109/ISPSD.1991.146082","DOIUrl":"https://doi.org/10.1109/ISPSD.1991.146082","url":null,"abstract":"The operation of 600 V forward blocking emitter switched thyristors (ESTs) has been experimentally demonstrated. The devices were fabricated using an IGBT baseline process with six masking steps. The forward I-V and turnoff characteristics have been measured and corroborated through two-dimensional numerical simulations. The output characteristics are close to a thyristor with an additional drop of about 0.5 V across the lateral MOSFET. Switching tests were performed up to a current density of 1000 A/cm/sup 2/ on single unit cells, and the measured turn-off times were about 7 mu s. A unique feature of the EST which is not seen in any other MOS-gated thyristor devices is saturation of thyristor current even after latch up of the main thyristor. This feature is very important for applications requiring current limiting and short circuit protection.<<ETX>>","PeriodicalId":127986,"journal":{"name":"[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116398399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
600 V, 25 A dielectrically-isolated power IC with vertical IGBT 具有垂直IGBT的600v, 25a介电隔离电源IC
[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 1991-04-22 DOI: 10.1109/ISPSD.1991.146062
T. Mizoguchi, T. Shirasawa, M. Mori, Y. Sugawara
{"title":"600 V, 25 A dielectrically-isolated power IC with vertical IGBT","authors":"T. Mizoguchi, T. Shirasawa, M. Mori, Y. Sugawara","doi":"10.1109/ISPSD.1991.146062","DOIUrl":"https://doi.org/10.1109/ISPSD.1991.146062","url":null,"abstract":"To obtain IGBT (insulated gate bipolar transistor) integrated large current power ICs which are more compact and reliable, a DI (dielectric isolation) application technology using a VIGBT (vertical IGBT) has been studied. As a result, an IC of the 600 V, 25 A class, presently the largest power rating of power ICs, has been achieved. The IGBT properties can be made identical to those of the discrete IGBT despite inherent restrictions of IC output devices. The IC also includes the control circuits. This DI method is known as a VLCS (vertical lateral composite structure) and is capable of integrating a large current vertical device. This method eliminates the latch-up problem of IGBTs using the junction isolation method.<<ETX>>","PeriodicalId":127986,"journal":{"name":"[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115559231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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