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[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs最新文献

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Effect of scaling on high-frequency switching efficiencies of power MOSFET's 标度对功率MOSFET高频开关效率的影响
[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 1991-04-22 DOI: 10.1109/ISPSD.1991.146072
K. Shenai
{"title":"Effect of scaling on high-frequency switching efficiencies of power MOSFET's","authors":"K. Shenai","doi":"10.1109/ISPSD.1991.146072","DOIUrl":"https://doi.org/10.1109/ISPSD.1991.146072","url":null,"abstract":"Summary form only given. The two-dimensional nature of junction and MOS capacitances of a power MOSFET is studied in detail as a function of terminal voltages. It is shown that the voltage dependencies of interelectrode capacitances in the near-threshold regime play a critical role in determining the high-frequency switching characteristics of power MOSFETs. Detailed two-dimensional modeling of the on-resistance, avalanche breakdown voltage, and interelectrode capacitances was performed to determine the effect of device scaling and to compare the performances of vertical vs. lateral low-voltage power DMOSFETs for high-voltage discrete and smart-power applications. Theoretical calculations are shown to be in excellent agreement with measured high-frequency switching performances of scaled power MOSFETs fabricated using advanced refractory metallizations.<<ETX>>","PeriodicalId":127986,"journal":{"name":"[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121430745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
MOSFET flyback-diode conduction and dV/dt effects in power ICs in low-voltage motor control applications 低压电机控制中功率集成电路中MOSFET反激二极管的导通和dV/dt效应
[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 1991-04-22 DOI: 10.1109/ISPSD.1991.146111
R.K. Williams, M. Cornell, J.A. Harnden
{"title":"MOSFET flyback-diode conduction and dV/dt effects in power ICs in low-voltage motor control applications","authors":"R.K. Williams, M. Cornell, J.A. Harnden","doi":"10.1109/ISPSD.1991.146111","DOIUrl":"https://doi.org/10.1109/ISPSD.1991.146111","url":null,"abstract":"In a power IC, the direct drive of a low-voltage motor by one or more MOSFET half-bridges results in inductive-flyback diode conduction during switching transitions. PISCES computer simulation reveals that this diode current in an integrated lateral MOSFET manifests itself as parasitic bipolar conduction where a substantial fraction of the carriers injected from the forward-biased drain-to-body junction is collected by the transistor's source. The physics of parasitic bipolar turn-off, or recovery, is shown to depend on the application. The resulting driving-point conditions can be classified into one of three possible diode recovery scenarios. In either natural or synchronously clamped recovery, high dV/dt is prevented by the inductive time constant of the motor. In forced recovery operation, fast diode turn-off and high dV/dt results from shoot-through between the recovering diode and the MOSFET within a given half-bridge. analysis reveals that a high dV/dt leading to minority carrier injection from the source slows the forced reverse-recovery time without leading to destructive snapback.<<ETX>>","PeriodicalId":127986,"journal":{"name":"[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128302668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Realization of high breakdown voltage (>700 V) in thin SOI devices 在薄SOI器件中实现高击穿电压(>700 V)
[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 1991-04-22 DOI: 10.1109/ISPSD.1991.146060
S. Merchant, E. Arnold, H. Baumgart, S. Mukherjee, H. Pein, R. Pinker
{"title":"Realization of high breakdown voltage (>700 V) in thin SOI devices","authors":"S. Merchant, E. Arnold, H. Baumgart, S. Mukherjee, H. Pein, R. Pinker","doi":"10.1109/ISPSD.1991.146060","DOIUrl":"https://doi.org/10.1109/ISPSD.1991.146060","url":null,"abstract":"The avalanche breakdown voltage of silicon on insulator (SOI) lateral diodes is investigated theoretically and experimentally. Theoretically, a condition is derived for achieving a uniform lateral electric field and thus optimizing the breakdown voltage. Using this condition, it is shown that, for SOI thicknesses below about 1 mu m, diode breakdown voltage increases with decreasing SOI layer thickness. Experimentally, breakdown voltages in excess of 700 V have been demonstrated for the first time on diodes having approximately 0.1- mu m-thick SOI layers and 2- mu m-thick buried oxide layers. The results obtained demonstrate the feasibility of making high-voltage thin-film SOI LDMOS transistors and, more importantly, the ability to integrate such devices with high-performance ultra-thin SOI CMOS circuits on a single chip.<<ETX>>","PeriodicalId":127986,"journal":{"name":"[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130733426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 216
Modeling of the transient ionizing radiation response of an inductively-loaded power MOSFET 电感负载功率MOSFET的瞬态电离辐射响应建模
[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 1991-04-22 DOI: 10.1109/ISPSD.1991.146088
A. Keshavarz, G. A. Franz, C. Hawkins
{"title":"Modeling of the transient ionizing radiation response of an inductively-loaded power MOSFET","authors":"A. Keshavarz, G. A. Franz, C. Hawkins","doi":"10.1109/ISPSD.1991.146088","DOIUrl":"https://doi.org/10.1109/ISPSD.1991.146088","url":null,"abstract":"The authors present a two-dimensional computer simulation of the radiation response of a power MOSFET device that uses the effect of the external load circuit in calculations. It makes it possible to observe the effects of the device structure, external circuitry, and biasing voltage on the transient radiation response of the device. The method is used to find important parameters such as the maximum induced current in the device or the maximum power dissipation under ionizing radiation. Based on the results, it can be decided if the device will be operating within its safety operating region when irradiated by a specific radiation pulse. The simulation can replace expensive and time-consuming laboratory testing with short-duration pulses.<<ETX>>","PeriodicalId":127986,"journal":{"name":"[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126528837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Self-isolation NMOS-DMOS technology for automotive low-side switches 汽车低侧开关的自隔离NMOS-DMOS技术
[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 1991-04-22 DOI: 10.1109/ISPSD.1991.146109
T. Fujihira, K. Yoshida, T. Mizuno, K. Sakurai, Y. Uchida
{"title":"Self-isolation NMOS-DMOS technology for automotive low-side switches","authors":"T. Fujihira, K. Yoshida, T. Mizuno, K. Sakurai, Y. Uchida","doi":"10.1109/ISPSD.1991.146109","DOIUrl":"https://doi.org/10.1109/ISPSD.1991.146109","url":null,"abstract":"A self-isolation NMOS-DMOS technology has been developed and successfully applied to an automotive intelligent power MOSFET low-side switch. Though self-isolation technology provides a cost-effective approach for intelligent power switches (IPSs), there are strict limitations for usable device structures and device connections. The limitations are tightest in the case of low-side IPSs. To overcome these limitations, an over-temperature detection circuit, a current limiting circuit, a dynamic clamping circuit, and an electrostatic surge protection method have been developed for self-isolation low-side IPSs. The principles of these circuits and experimental results are presented together with an outline of self-isolation NMOS-DMOS technology. The applicability of self-isolation NMOS-DMOS technology to high voltage and/or IGBT (insulated-gate bipolar transistor) type IPSs is also demonstrated.<<ETX>>","PeriodicalId":127986,"journal":{"name":"[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs","volume":"162 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124535405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 1500 V IGBT with a self-aligned DMOS structure for high resolution CRT operated up to 100 kHz 一种具有自对准DMOS结构的1500 V IGBT，用于高分辨率CRT，工作频率高达100 kHz
[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 1991-04-22 DOI: 10.1109/ISPSD.1991.146103
M. Mori, Y. Nakano, Y. Yasuda, T. Yatsuo, Y. Sugawara
{"title":"A 1500 V IGBT with a self-aligned DMOS structure for high resolution CRT operated up to 100 kHz","authors":"M. Mori, Y. Nakano, Y. Yasuda, T. Yatsuo, Y. Sugawara","doi":"10.1109/ISPSD.1991.146103","DOIUrl":"https://doi.org/10.1109/ISPSD.1991.146103","url":null,"abstract":"The authors present a 1500 V insulated gate bipolar transistor (IGBT) with a self-aligned DMOS structure (SA-DMOS) using a phosphosilicate glass (PSG) sidewall for a horizontal deflection output transistor in a high-resolution CRT (cathode ray tube). The scaled-down MOS structure, such as the SA-DMOS with a 5 mu m distance between the polysilicon gates, was useful for even a high blocking voltage IGBT to realize a low forward voltage drop and small turn-off loss. A 1500 V SA-DMOS IGBT having a chip size of 8*8 mm/sup 2/, a forward voltage drop of 4.0 V at a forward current of 6 A, and a turn-off loss of 33 mu J has been fabricated. The power loss of the SA-DMOS IGBT was 2.5 times lower than that of a conventional power MOSFET at a high frequency of up to 100 kHz.<<ETX>>","PeriodicalId":127986,"journal":{"name":"[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127634682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
High switching speed 1500 V IGBT for CRT deflection circuit 高开关速度1500v，用于CRT偏转电路
[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 1991-04-22 DOI: 10.1109/ISPSD.1991.146108
Y. Seki, Y. Hoshi, H. Shimabukuro, N. Suganuma, A. Nishiura, Y. Uchida
{"title":"High switching speed 1500 V IGBT for CRT deflection circuit","authors":"Y. Seki, Y. Hoshi, H. Shimabukuro, N. Suganuma, A. Nishiura, Y. Uchida","doi":"10.1109/ISPSD.1991.146108","DOIUrl":"https://doi.org/10.1109/ISPSD.1991.146108","url":null,"abstract":"A novel 1500 V IGBT (insulated gate bipolar transistor) was developed for the CRT horizontal deflection circuit. The authors clarify the device characteristics needed for the horizontal deflection circuit and demonstrate the 1500 V IGBT specially designed for this application. In order to make it possible to operate in the high frequency region, the device design and process conditions in the IBGT, i.e., the surface MOS-gate structure, the n/sup +/ buffer layer structure, and the lifetime killer control, were optimized. It was confirmed that this 1500 V IGBT was driven and operated up to a 70 kHz deflection frequency.<<ETX>>","PeriodicalId":127986,"journal":{"name":"[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129223237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Impact ionization in saturated high-voltage LDD lateral DMOS FETs 饱和高压LDD横向DMOS场效应管的冲击电离
[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 1991-04-22 DOI: 10.1109/ISPSD.1991.146090
M. Cornell, R.K. Williams, H. Yilmaz
{"title":"Impact ionization in saturated high-voltage LDD lateral DMOS FETs","authors":"M. Cornell, R.K. Williams, H. Yilmaz","doi":"10.1109/ISPSD.1991.146090","DOIUrl":"https://doi.org/10.1109/ISPSD.1991.146090","url":null,"abstract":"The mechanism of impact ionization in high-voltage lightly-doped drain (LDD) lateral DMOS FETs is analyzed. Two-carrier PISCES simulations confirm a reduction in both sustaining voltage and output impedance compared to zero or one-carrier simulations. Maximum impact ionization is not observed at the peak field location, but as an interaction of subsurface conduction and a high-field region located under the gate field plate. An extended gate field plate is shown to reduce pre-avalanche impact ionization without substantially degrading avalanche breakdown. Breakdown optimizing design methodologies are shown to be inadequate to guarantee minimal impact ionization. Finally, the reduction in saturated output impedance predicted by PISCES is confirmed on 500-V fabricated devices.<<ETX>>","PeriodicalId":127986,"journal":{"name":"[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128747129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Switching loss analysis of shorted drain non punch-through and punch-through type IGBTs in voltage resonant circuit 电压谐振电路中短路漏极非穿通型和穿通型igbt开关损耗分析
[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 1991-04-22 DOI: 10.1109/ISPSD.1991.146104
N. Iwamuro, Y. Hoshi, Y. Seki, N. Kumagai
{"title":"Switching loss analysis of shorted drain non punch-through and punch-through type IGBTs in voltage resonant circuit","authors":"N. Iwamuro, Y. Hoshi, Y. Seki, N. Kumagai","doi":"10.1109/ISPSD.1991.146104","DOIUrl":"https://doi.org/10.1109/ISPSD.1991.146104","url":null,"abstract":"The dissipated turn-off losses of shorted drain non-punch-through and punch-through type IGBTs (insulated-gate bipolar transistors) are investigated for voltage resonant circuit application. These characteristics are analyzed experimentally and calculated by using a two-dimensional device simulator. It is shown that the shorted drain structure is not effective for decreasing the dissipated loss, whereas the optimized punch-through type IGBT is suitable for this circuit application.<<ETX>>","PeriodicalId":127986,"journal":{"name":"[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126822724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
The vertical IGBT with an implanted buried layer 具有植入埋层的垂直IGBT
[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 1991-04-22 DOI: 10.1109/ISPSD.1991.146102
S. Eranen, M. Blomberg
{"title":"The vertical IGBT with an implanted buried layer","authors":"S. Eranen, M. Blomberg","doi":"10.1109/ISPSD.1991.146102","DOIUrl":"https://doi.org/10.1109/ISPSD.1991.146102","url":null,"abstract":"The properties of vertical IGBT (insulated-gate bipolar transistor) test structures with implanted, self-aligned, boron doped buried layers are considered. In the case examined, the buried layers form retrograde p-type regions under the n-type sources of the IGBT. The modifications of the normal IGBT process, which are needed for the fabrication of the buried layers, are described. The process parameters and process steps which are relevant in the context of the buried layers are discussed. Some results from 1-D and 2-D process simulations are shown. Finally, the results of electrical measurements on test IGBTs with several kinds of buried layers and without the buried layers are reported. It is demonstrated that the latch-up current can be dramatically improved with the addition of the buried layer, whereas the forward conduction properties are independent of the buried layers.<<ETX>>","PeriodicalId":127986,"journal":{"name":"[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126667961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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