[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs最新文献_第5页

Quasi-dielectrically isolated bipolar junction transistor with sub-collector fabricated using silicon selective epitaxy 采用硅选择性外延技术制备具有副集电极的准介电隔离双极结晶体管

[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 1991-04-22 DOI: 10.1109/ISPSD.1991.146099

P. Gilbert, G. Neudeck, J. Denton, S. Duey

引用次数: 1

Correlation between local segment characteristics and dynamic current redistribution in GTO power thyristors GTO功率晶闸管局部段特性与动态电流重分布的关系

[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 1991-04-22 DOI: 10.1109/ISPSD.1991.146081

C. Johnson, A. Jaecklin, P. Palmer, P. Streit

{"title":"Correlation between local segment characteristics and dynamic current redistribution in GTO power thyristors","authors":"C. Johnson, A. Jaecklin, P. Palmer, P. Streit","doi":"10.1109/ISPSD.1991.146081","DOIUrl":"https://doi.org/10.1109/ISPSD.1991.146081","url":null,"abstract":"The peak controllable current of a typical GTO (gate turn-off) thyristor is limited by the redistribution of anode current, occurring during the turn-off transient. This behavior is investigated in practical large-area GTOs (600 A, 1600 V) by comparing the static and dynamic characteristics of the individual device segments with turn-off current density estimates for the complete device. Reverse gate-cathode breakdown voltage, forward on-state voltage, and storage time are mapped using an automatic probing system while the current density estimates are obtained using a magnetic field measurement technique. Good correlation is found between the current density peaks, the segment measurement, and variations in the mesa etching depth across the processed wafer. Conditions are established which relate the distribution of current density peaks and segment characteristics to the realization of a near-perfect GTO technology. The behavior of the current density distribution during the current fall and early tail period is related to the onset of of filamentation and subsequent device failure.<<ETX>>","PeriodicalId":127986,"journal":{"name":"[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131452216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

P-ch and N-ch IGBTs for push-pull circuit in driver ICs 驱动ic中推挽电路的P-ch和N-ch igbt

[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 1991-04-22 DOI: 10.1109/ISPSD.1991.146068

K. Tsuchiya

引用次数: 0

Optimization of the breakdown voltage in LDMOS transistors using internal field rings 利用内场环优化LDMOS晶体管击穿电压

[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 1991-04-22 DOI: 10.1109/ISPSD.1991.146087

A. Nezar, C. Salama

{"title":"Optimization of the breakdown voltage in LDMOS transistors using internal field rings","authors":"A. Nezar, C. Salama","doi":"10.1109/ISPSD.1991.146087","DOIUrl":"https://doi.org/10.1109/ISPSD.1991.146087","url":null,"abstract":"It is shown that field rings in the drift region of LDMOS (lateral double diffused MOS) transistors can be used to reduce the electric field at the Si/SiO/sub 2/ interface and increase the breakdown voltage of the structure. A first order analytical approach shows the upper limit of the position of the ring with respect to the channel, and the doping concentration within the ring to increase the breakdown voltage. A 2-D numerical calculation of the breakdown voltage and on-resistance of the LDMOS transistor is presented. The results, which support the analytical approach, allow the designer to use simple design rules for the implantation of high-voltage LDMOS transistors on thick epitaxial layers. A potential improvement of the breakdown voltage arises if the distance between the channel and the field ring is equal to the field plate length and the doping concentration in the ring satisfies a specified equation. Doubling the breakdown voltage is associated with a 25% increase in device area. The on-resistance depends mainly on the field ring position with respect to the channel. A good tradeoff between the breakdown voltage and on-resistance is obtained when the channel-ring distance is equal to the field plate length.<<ETX>>","PeriodicalId":127986,"journal":{"name":"[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130229752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Electrothermal simulation of power semiconductor devices 功率半导体器件的电热模拟

[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 1991-04-22 DOI: 10.1109/ISPSD.1991.146074

P. A. Gough, P. Walker, K.R. Whight

引用次数: 12

CMOS compatible 250 V lateral insulated base transistors CMOS兼容250v横向绝缘基极晶体管

[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 1991-04-22 DOI: 10.1109/ISPSD.1991.146094

E. M. Sankara Narayanan, G. Amaratunga, W. Milne, Q. Huang

{"title":"CMOS compatible 250 V lateral insulated base transistors","authors":"E. M. Sankara Narayanan, G. Amaratunga, W. Milne, Q. Huang","doi":"10.1109/ISPSD.1991.146094","DOIUrl":"https://doi.org/10.1109/ISPSD.1991.146094","url":null,"abstract":"The performance of various insulated base transistors implemented with a digital CMOS compatible high-voltage integrated circuit process was demonstrated. Design modifications in the lateral insulated base transistor (LIBT) structures have been proposed, and the performance of the improved LIBTs has been compared with that of a conventional LIBT structure. These modifications are based on the effective use of charge-controlled n/sup +/ buried layers to improve the on-state capability of the device. Four different types of LIBT structures have been fabricated and tested. The experimental analysis of the CMOS-compatible LIBTs discussed shows that the n/sup +/ buried layer placed under the p well plays a crucial role in improving the device performance. The improved LIBT structure with n/sup +/ buried layers incorporated near the collector and the p well regions shows the best characteristics with high voltage blocking capability, low specific on-resistance, and a low turn-off delay. A specific on-resistance of 0.016 Omega -cm/sup 2/ and a turn-off delay of 90 ns were obtained in the improved LIBT structure, which can withstand up to 250 V.<<ETX>>","PeriodicalId":127986,"journal":{"name":"[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129970845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Analysis of silicon carbide power device performance 碳化硅功率器件性能分析

[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 1991-04-22 DOI: 10.1109/ISPSD.1991.146093

M. Bhatnagar, B. J. Baliga

引用次数: 25