Optimization of the breakdown voltage in LDMOS transistors using internal field rings

A. Nezar, C. Salama
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引用次数: 1

Abstract

It is shown that field rings in the drift region of LDMOS (lateral double diffused MOS) transistors can be used to reduce the electric field at the Si/SiO/sub 2/ interface and increase the breakdown voltage of the structure. A first order analytical approach shows the upper limit of the position of the ring with respect to the channel, and the doping concentration within the ring to increase the breakdown voltage. A 2-D numerical calculation of the breakdown voltage and on-resistance of the LDMOS transistor is presented. The results, which support the analytical approach, allow the designer to use simple design rules for the implantation of high-voltage LDMOS transistors on thick epitaxial layers. A potential improvement of the breakdown voltage arises if the distance between the channel and the field ring is equal to the field plate length and the doping concentration in the ring satisfies a specified equation. Doubling the breakdown voltage is associated with a 25% increase in device area. The on-resistance depends mainly on the field ring position with respect to the channel. A good tradeoff between the breakdown voltage and on-resistance is obtained when the channel-ring distance is equal to the field plate length.<>
利用内场环优化LDMOS晶体管击穿电压
结果表明,在LDMOS(横向双扩散MOS)晶体管的漂移区存在场环,可以减小Si/SiO/sub - 2/界面处的电场,提高结构的击穿电压。一阶解析方法显示了环相对于通道位置的上限,以及环内的掺杂浓度以增加击穿电压。给出了LDMOS晶体管击穿电压和导通电阻的二维数值计算方法。结果支持分析方法,允许设计者使用简单的设计规则在厚外延层上植入高压LDMOS晶体管。如果通道和场环之间的距离等于场板长度,并且环中的掺杂浓度满足指定的方程,则击穿电压可能会提高。击穿电压加倍与器件面积增加25%有关。导通电阻主要取决于场环相对于通道的位置。当沟道环距离等于场极板长度时,击穿电压和导通电阻之间得到了很好的平衡
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