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[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs最新文献

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Optimization of the MPS rectifier via variation of Schottky region area 通过改变肖特基区面积来优化MPS整流器
[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 1991-04-22 DOI: 10.1109/ISPSD.1991.146078
Shen-Hang Tu, B. J. Baliga
{"title":"Optimization of the MPS rectifier via variation of Schottky region area","authors":"Shen-Hang Tu, B. J. Baliga","doi":"10.1109/ISPSD.1991.146078","DOIUrl":"https://doi.org/10.1109/ISPSD.1991.146078","url":null,"abstract":"The authors discuss the optimization of the switching characteristics of the MPS (merged PIN/Schottky) rectifier by varying the relative area of the P-N junction and Schottky regions. Extensive two-dimensional numerical simulations have been performed of the forward condition and reverse recovery switching characteristics. It has been found that a trade-off curve between the forward voltage drop and the reverse recovery time can be obtained by varying the area of the Schottky region, while maintaining a constant minority carrier lifetime. This trade-off curve is superior to that obtained for the PIN rectifier using lifetime control. Experimental data that corroborate this theoretical prediction have been obtained by fabrication of 700 V devices. This method of performing the trade-off between the forward drop and the turn-off time has the advantage that it can be done by device design without the problems and additional processing cost associated with lifetime control.<<ETX>>","PeriodicalId":127986,"journal":{"name":"[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129379969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
An application of MSSD to dielectrically isolated intelligent power IC MSSD在介质隔离智能电源集成电路中的应用
[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 1991-04-22 DOI: 10.1109/ISPSD.1991.146063
T. Aso, H. Mizuide, T. Usui, K. Akahane, N. Ishikawa, I. Hide, Y. Maeda
{"title":"An application of MSSD to dielectrically isolated intelligent power IC","authors":"T. Aso, H. Mizuide, T. Usui, K. Akahane, N. Ishikawa, I. Hide, Y. Maeda","doi":"10.1109/ISPSD.1991.146063","DOIUrl":"https://doi.org/10.1109/ISPSD.1991.146063","url":null,"abstract":"The authors describe the application of MSSD (molten silicon spraying deposition) to a dielectrically isolated intelligent power IC. This IC requires a thick silicon layer with low resistivity as its main current flow region. A 500 mu m thick single silicon layer with heavily doped phosphorus ( rho =0.02 Omega -cm) was successfully deposited in a few minutes by using the MSSD method. A vertical n-p-h transistor has been fabricated by this method and has shown good I-V characteristics.<<ETX>>","PeriodicalId":127986,"journal":{"name":"[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127496361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Performance of 200 V CMOS compatible auxiliary cathode lateral insulated gate transistors 200v CMOS兼容辅助阴极侧绝缘栅极晶体管的性能
[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 1991-04-22 DOI: 10.1109/ISPSD.1991.146077
E. M. Sankara Narayanan, G. Amaratunga, W. Milne, Q. Huang
{"title":"Performance of 200 V CMOS compatible auxiliary cathode lateral insulated gate transistors","authors":"E. M. Sankara Narayanan, G. Amaratunga, W. Milne, Q. Huang","doi":"10.1109/ISPSD.1991.146077","DOIUrl":"https://doi.org/10.1109/ISPSD.1991.146077","url":null,"abstract":"The authors report the performance of various anode-shorted auxiliary cathode lateral insulated gate transistor (ACLIGT) structures fabricated using a 2.5 mu m digital CMOS compatible HVIC process. The reverse breakdown voltage of the ACLIGT is comparable to that of an equivalent anode shorted lateral insulated gate transistor (LIGT). The results indicate that, by placing an auxiliary cathode and an extended p-buried layer of an anode-shorted LIGT, the holes flowing into the p-well can be diverted to overcome the latch-up problems of the LIGT in an ACLIGT. The LIGT shows latch-up at 140 mA, which corresponds to a current density of 340 A/cm/sup 2/ while the ACLIGT structures do not show latch-up. The measured turn-off characteristics of the ACLIGT reveal a turn-off time of less than 250 ns while an equivalent LIGT shows a turn-off time of 350 ns.<<ETX>>","PeriodicalId":127986,"journal":{"name":"[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127334780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Integration of a 200 V, 60 MHz lateral PNP transistor with emitter-base self-aligned to polysilicon into a high voltage BiCMOS process 集成一个200v, 60mhz横向PNP晶体管，发射极基极自对准多晶硅到高压BiCMOS工艺
[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 1991-04-22 DOI: 10.1109/ISPSD.1991.146066
M. Masquelier, D. Okada
{"title":"Integration of a 200 V, 60 MHz lateral PNP transistor with emitter-base self-aligned to polysilicon into a high voltage BiCMOS process","authors":"M. Masquelier, D. Okada","doi":"10.1109/ISPSD.1991.146066","DOIUrl":"https://doi.org/10.1109/ISPSD.1991.146066","url":null,"abstract":"A 200-V BV/sub CEO/ (breakdown voltage) lateral PNP transistor with improved frequency response over conventional designs has been designed and fabricated, utilizing only the existing layers of a BiCMOS process suitable for power integrated circuits. The self-alignment of the emitter and base implants to the edge of a polysilicon field plate provides a narrow, graded base region with a very repeatable base width. The 2.5 mu m base width provides a f/sub tau / (unity-gain frequency) value that is 40 times larger than that of conventional lateral PNPs with the same BV/sub CEO/. During layout the extended collector length is drawn only as long as is necessary to achieve the required breakdown voltage, resulting in a significant area savings, minimal collector resistance, and reduced power dissipation.<<ETX>>","PeriodicalId":127986,"journal":{"name":"[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131641087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An analytical IGBT model for power circuit simulation 一种用于功率电路仿真的解析式IGBT模型
[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 1991-04-22 DOI: 10.1109/ISPSD.1991.146071
Z. Shen, T. Chow
{"title":"An analytical IGBT model for power circuit simulation","authors":"Z. Shen, T. Chow","doi":"10.1109/ISPSD.1991.146071","DOIUrl":"https://doi.org/10.1109/ISPSD.1991.146071","url":null,"abstract":"On the basis of the physical picture obtained by a detailed two-dimensional numerical simulation, an analytical CAD (computer-aided design) model for an IGBT (insulated-gate bipolar transistor) is developed which has sufficient flexibility to account for the unique characteristics of IGBT operation, while still retaining a mathematically simple form with readily extractable model parameters. The static model has been implemented in the circuit simulator SPICE. A systematic method of DC model parameter extraction is developed based on the parameter optimization program TOPEX. A set of model parameters extracted for a n-channel 600-V, symmetric IGBT is shown. Good agreement has been obtained between the simulation results and measurements.<<ETX>>","PeriodicalId":127986,"journal":{"name":"[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs","volume":"156 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124384535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Numerical analysis of switching in the IGBT triggered thyristor IGBT触发晶闸管开关的数值分析
[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 1991-04-22 DOI: 10.1109/ISPSD.1991.146083
H. Sumida, K. Ueno, N. Iwamuro, S. Tagami
{"title":"Numerical analysis of switching in the IGBT triggered thyristor","authors":"H. Sumida, K. Ueno, N. Iwamuro, S. Tagami","doi":"10.1109/ISPSD.1991.146083","DOIUrl":"https://doi.org/10.1109/ISPSD.1991.146083","url":null,"abstract":"A monolithic power switching device structure for a MOS-controlled thyristor, called the IGBT (insulated gate bipolar transistor) triggered thyristor (ITT), is presented. In this device, a thyristor element is integrated into an IGBT structure and the minority carriers of the IGBT supply the trigger current of the thyristor. The target of this device is to achieve lower forward voltage than an IGBT without drastic deterioration of the turn-off characteristics. Numerical results on the ITT performance, and the on-state and the turn-off characteristics under inductive loads are described as compared with a conventional IGBT. Two-dimensional simulation results indicate that the forward voltage drop is lower than that of the IGBT and the MOS-gate turn-off capability is retained under inductive loads. The forward voltage drop at an on-state current of 100 A/cm/sup 2/ is 1.5 V, which is about 0.5 V lower than that of the IGBT, and the turn-off time is 0.19 mu s, which is a little longer than that of the IGBT.<<ETX>>","PeriodicalId":127986,"journal":{"name":"[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs","volume":"6 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114037316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Fast LIGBT switching due to plasma confinement through pulse width control 通过脉冲宽度控制等离子体约束的快速光开关
[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 1991-04-22 DOI: 10.1109/ISPSD.1991.146076
I. Wacyk, R. Jayaraman, L. Casey, J. Sin
{"title":"Fast LIGBT switching due to plasma confinement through pulse width control","authors":"I. Wacyk, R. Jayaraman, L. Casey, J. Sin","doi":"10.1109/ISPSD.1991.146076","DOIUrl":"https://doi.org/10.1109/ISPSD.1991.146076","url":null,"abstract":"The authors have examined the initial turn-on dynamics of the LIGBT (lateral insulated gate bipolar transistor) and shown through data and simulations that the LIGBT achieves effective conductivity modulation within approximately 200 ns of turn-on. At this time, the parasitic vertical PNP is saturated and the on-voltage has virtually reached a minimum. Beyond 200 ns, it is shown that only a marginal improvement in the on-voltage is obtained and at substantial cost in terms of switching speed. This observation was exploited by implementing a constant on-time PWM up-converter operating with 94% efficiency at 200 kHz. This demonstrated viable LIGBT operation at a frequency well above the range that conventional wisdom suggests.<<ETX>>","PeriodicalId":127986,"journal":{"name":"[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116549132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
New method of carrier lifetime measurement for accurate power device simulation 载波寿命测量的新方法，用于精确的功率器件仿真
[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 1991-04-22 DOI: 10.1109/ISPSD.1991.146092
A. Yahata, Y. Yamaguchi, A. Nakagawa, H. Ohashi
{"title":"New method of carrier lifetime measurement for accurate power device simulation","authors":"A. Yahata, Y. Yamaguchi, A. Nakagawa, H. Ohashi","doi":"10.1109/ISPSD.1991.146092","DOIUrl":"https://doi.org/10.1109/ISPSD.1991.146092","url":null,"abstract":"A method of carrier lifetime measurement is proposed for accurate power device simulation. It requires the value of independent electron ( tau /sub n/) and hole ( tau /sub p/) lifetimes. Reverse recovery time and the electron-beam-induced junction current of Si p/sup +/nn/sup +/ diodes were measured to obtain the high injection carrier lifetimes ( tau /sub H/) and tau /sub p/, respectively. tau /sub n/ were deduced by extracting tau /sub p/ from tau /sub H/ on the basis of Shockley-Read-Hall theory. tau /sub n/ of the nonirradiated samples and samples irradiated at electron fluxes of 3*10/sup 13/ cm/sup -2/, 5*10/sup 13/ cm/sup -2/, and 7*10/sup 13/ cm/sup -2/ were 3.1 mu s, 600 ns, 360 ns, and 300 ns, respectively. For the same samples, tau /sub p/ were 2.6 mu s, 72 ns, 51 ns, and 33 ns, respectively. These results indicate that tau /sub n// tau /sub p/ values are about one for nonirradiated samples and seven to nine for electron-irradiated samples.<<ETX>>","PeriodicalId":127986,"journal":{"name":"[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132092825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Application of dielectric isolation technology based on soot bonding 基于烟尘键合的介电隔离技术的应用
[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 1991-04-22 DOI: 10.1109/ISPSD.1991.146100
R. Sawada, H. Nakada
{"title":"Application of dielectric isolation technology based on soot bonding","authors":"R. Sawada, H. Nakada","doi":"10.1109/ISPSD.1991.146100","DOIUrl":"https://doi.org/10.1109/ISPSD.1991.146100","url":null,"abstract":"A soot bonding method has been developed that solves the economic and limited-diameter problems associated with the conventional dielectrically isolated substrate. In this method, the Si-B-O soot particles used as adhesive agents are generated by essentially the same flame-hydrolysis technology used for fabricating optical waveguides. This soot bonding method is effective even for joining a surface with deep V-grooves or trenches, as well as for rough poly-Si-deposited surfaces. The ability to bond substrates with any joining surface conditions is expected to lead to wide application of this process and to a reduction of the steps, resulting in cost reduction.<<ETX>>","PeriodicalId":127986,"journal":{"name":"[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125044798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
N-ch IGBT with high reverse blocking capability for multipoint differential line drivers 多点差分线路驱动器具有高反向阻塞能力的N-ch IGBT
[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 1991-04-22 DOI: 10.1109/ISPSD.1991.146069
N. Fujishima, Y. Yano, G. Tada, K. Tsuchiya
{"title":"N-ch IGBT with high reverse blocking capability for multipoint differential line drivers","authors":"N. Fujishima, Y. Yano, G. Tada, K. Tsuchiya","doi":"10.1109/ISPSD.1991.146069","DOIUrl":"https://doi.org/10.1109/ISPSD.1991.146069","url":null,"abstract":"A 2 mu m rule DMOS/CMOS compatible IGBT (insulated-gate bipolar transistor) with high reverse blocking capability has been developed for multipoint differential line drivers. Remarkable improvement of the reverse blocking capability and large latch-up current are achieved due to the formation of the wide N-base, the heavily doped N-buffer, and the P-well around the P-base. The effect of the conductivity modulation, arising from the injected holes, is compared with the DMOSFET in series with a P- nu -N diode.<<ETX>>","PeriodicalId":127986,"journal":{"name":"[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116158063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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