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VERVE: A framework for variation-aware energy efficient synthesis of NoC-based MPSoCs with voltage islands VERVE:一个具有电压岛的基于noc的mpsoc的变化感知节能合成框架
International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523673
N. Kapadia, S. Pasricha
{"title":"VERVE: A framework for variation-aware energy efficient synthesis of NoC-based MPSoCs with voltage islands","authors":"N. Kapadia, S. Pasricha","doi":"10.1109/ISQED.2013.6523673","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523673","url":null,"abstract":"With feature sizes far below the wavelength of light, variations in fabrication processes are becoming more common and can lead to unpredictable behavior in modern multiprocessor system-on-chip (MPSoC) designs. The design costs associated with margining required to overcome this unpredictability can be prohibitively high. System-level design approaches that are aware of these variations can be crucial for designing energy-efficient systems. We note that by performing voltage island placement appropriately, the two major unintended consequences of variations on the circuit characteristics (altered delay and power dissipation) can be traded-off, in order to minimize overall system energy. To this end, we propose a novel design-time system-level synthesis framework that is cognizant of process variations while mapping cores operating at specific supply voltages to a die and allocating communication routes on a 2D-mesh network-on-chip (NoC) topology for optimal energy-efficiency. Our experiments with real-world and synthetic application benchmarks show that our framework achieves 3.4% savings in computation energy and 19% savings in communication energy compared to the best known prior work on NoC-based MPSoC synthesis that considers process variations.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126878101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
RF passive device modeling and characterization in 65nm CMOS technology 65纳米CMOS技术下射频无源器件的建模与表征
International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523680
E. Lourandakis, S. Stefanou, K. Nikellis, S. Bantas
{"title":"RF passive device modeling and characterization in 65nm CMOS technology","authors":"E. Lourandakis, S. Stefanou, K. Nikellis, S. Bantas","doi":"10.1109/ISQED.2013.6523680","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523680","url":null,"abstract":"Rapid passive device modeling is discussed in this work based on test structures fabricated in a 65nm CMOS process with M1-M9 copper metal layers and one aluminum metal layer AP. Capacitance extraction for overlapping microstrips and shielded microstrip structures is investigated. Individual capacitances are modeled in terms of area and fringe components, either between microstrips or between microstrips and silicon substrate. Good correlation to silicon data is achieved for the fabricated test structures. The validity of the proposed model is also investigated for complex passive devices such as inductors and interdigitated capacitors. Device metrics for both types of passive devices are investigated and compared to measured silicon data. Good agreement is achieved in all cases proving the accuracy of the proposed modeling approach.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131890909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Wire delay variability in nanoscale technology and its impact on physical design 纳米技术中的导线延迟变异性及其对物理设计的影响
International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523671
S. Nassif, Gi-Joon Nam, Shayak Banerjee
{"title":"Wire delay variability in nanoscale technology and its impact on physical design","authors":"S. Nassif, Gi-Joon Nam, Shayak Banerjee","doi":"10.1109/ISQED.2013.6523671","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523671","url":null,"abstract":"Current technology scaling trends are changing the character of wire delay variability. The distribution of wire delay is asymmetric, with a long positive tail which can be as much as 2X longer than the negative tail. This is due to the geometry of these wires, where the aspect ratio is biased towards tall thin wire cross-sections, as well as manufacturing induced variations particularly from lithography. These trends are important for timing closure, whether done via corner-based or statistical analysis. In this paper, we explore these trends, demonstrate their impact in a modern 32nm CMOS design, and suggest ways in which this trend can be managed and reduced. Particularly, through physical synthesis optimization on industrial designs, we show how these trends/observations can be utilized to produce more reliable designs. As the interconnect scaling lags behind the device scaling, the importance of wire variability will grow further in the future technology nodes.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134065246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Performance entitlement by exploiting transistor's BTI recovery 利用晶体管的BTI恢复的性能权利
International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523632
S. Arasu, M. Nourani, V. Reddy, J. Carulli
{"title":"Performance entitlement by exploiting transistor's BTI recovery","authors":"S. Arasu, M. Nourani, V. Reddy, J. Carulli","doi":"10.1109/ISQED.2013.6523632","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523632","url":null,"abstract":"The inherent problem in signal probability (α) prediction has limited the scope of exploiting the transistor's BTI recovery at circuit level. In this paper, we present a design-for-reliability (DFR) methodology for digital designs, BTI_Refresh, that instead of relying on predicting α, sets it to a known value (~0.5) such that the BTI stress effects are alleviated and a predicted recovery effect could be guaranteed at circuit level. The technique can be applied equally to both NBTI and PBTI. Experimental results using Cadence Relxpert on critical paths extracted from industry designs show that with a negligible power, area overhead, a significant improvement (50%) in the total degradation of critical path performance with respect to end-of-life models is achievable.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134152868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Geostatistics inspired fast layout optimization of nanoscale CMOS phase locked loop 地统计学启发了纳米级CMOS锁相环的快速布局优化
International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523664
Oghenekarho Okobiah, S. Mohanty, E. Kougianos
{"title":"Geostatistics inspired fast layout optimization of nanoscale CMOS phase locked loop","authors":"Oghenekarho Okobiah, S. Mohanty, E. Kougianos","doi":"10.1109/ISQED.2013.6523664","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523664","url":null,"abstract":"In this paper, we present a geostatistical method for design and optimization of analog and mixed signal circuits design illustrated with the design of phase locked loop (PLL) systems used in Wide Area Network (WAN) and Private Mobile Radio (PMR) applications. The proposed method incorporates the use of a geostatistic based metamodeling technique (Kriging) and optimization algorithm (gravitational search algorithm) and is compared to similar approaches. The results show that the geostatistical methods provide more accurate metamodels and more efficient optimization design techniques. To the best of the authors' knowledge, this is the first geostatistical method for metamodeling and optimization of PLL designs. The proposed optimization could achieve 79% reduction in PLL power with 4% reduction in locking time without any area penalty.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134450291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Analytical modeling and numerical simulations of temperature field in TSV-based 3D ICs 基于tsv的三维集成电路温度场分析建模与数值模拟
International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523585
Y. Shiyanovskii, C. Papachristou, Cheng-Wen Wu
{"title":"Analytical modeling and numerical simulations of temperature field in TSV-based 3D ICs","authors":"Y. Shiyanovskii, C. Papachristou, Cheng-Wen Wu","doi":"10.1109/ISQED.2013.6523585","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523585","url":null,"abstract":"Three dimensional (3D) integrated circuit (IC) technology is emerging as a potential alternative to address the physical limitations in miniaturization of the current 2D semiconductor devices. The 3D IC integration is based on the concept of through-silicon vias (TSV) and vertical stacking of multiple active layers. TSV-based 3D IC's offer significant advantages in performance due to reduction in interconnect lengths, and design flexibility in vertical floor planning. However, a critical challenge for the 3D IC integration is thermal management. In this paper, we present a new analytical 3D model and numerical simulations of the temperature field for the 3D chip using the formalism of inplane orthogonal functions. The model takes into account heat transfer through external surfaces of the chip, inhomogeneous electric heating within the layer (localized heating), inter layer heat transfer with possible inhomogeneous TSV placement and micro channel cooling. Our simulations implement the proposed model and demonstrate its viability and computational efficiency for temperature field optimization.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131996516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
LMgr: A low-M emory global router with dynamic topology update and bending-aware optimum path search LMgr:一个具有动态拓扑更新和弯曲感知最优路径搜索的低内存全局路由器
International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523615
Jingwei Lu, Chiu-Wing Sham
{"title":"LMgr: A low-M emory global router with dynamic topology update and bending-aware optimum path search","authors":"Jingwei Lu, Chiu-Wing Sham","doi":"10.1109/ISQED.2013.6523615","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523615","url":null,"abstract":"Global routing remains a fundamental physical design problem. We observe that large circuits cause high memory cost1, and modern routers could not optimize the routing path of each two-pin subnet. In this paper, (1) we develop a dynamic topology update technique to improve routing quality (2) we improve the memory efficiency with negligible performance overhead (3) we prove the non-optimality of traditional maze routing algorithm (4) we develop a novel routing algorithm and prove that it is optimum (5) we design a new global router, LMgr, which integrates all the above techniques. The experimental results on the ISPD 2008 benchmark suite show that LMgr could outperform NTHU2.0, NTUgr, FastRoute3.0 and FGR1.1 on solution quality in 13 out of 16 benchmarks and peak memory cost in 15 out of 16 benchmarks, the average memory reduction over all the benchmarks is up to 77%.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133795119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Flexible data allocation for scratch-pad memories to reduce NBTI effects 灵活的数据分配的刮擦板存储器，以减少NBTI的影响
International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523591
Dimitra Papagiannopoulou, Patipan Prasertsom, R. I. Bahar
{"title":"Flexible data allocation for scratch-pad memories to reduce NBTI effects","authors":"Dimitra Papagiannopoulou, Patipan Prasertsom, R. I. Bahar","doi":"10.1109/ISQED.2013.6523591","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523591","url":null,"abstract":"Negative Bias Temperature Instability (NBTI) is a major reliability issue in nanoscale VLSI systems. Previous work has shown how the exploitation of conventional optimization techniques can reduce the NBTI-induced aging in cache memories. Other works have proposed approaches that incorporate software directed data allocation strategies to partially recover from NBTI-induced aging in Scratchpad Memories (SPM). In this paper, we extend the existing software approach in order to enhance the memory allocation flexibility and make it more appropriate for real embedded applications. Simulation results demonstrate how our proposed data allocation strategies can help mitigate the NBTI-induced aging effects, as well as reduce the leakage energy consumption on scratch-pad memories.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131614690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
SRAM bit-line electromigration mechanism and its prevention scheme SRAM位线电迁移机制及其预防方案
International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523624
Zhong Guan, M. Marek-Sadowska, S. Nassif
{"title":"SRAM bit-line electromigration mechanism and its prevention scheme","authors":"Zhong Guan, M. Marek-Sadowska, S. Nassif","doi":"10.1109/ISQED.2013.6523624","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523624","url":null,"abstract":"In this paper, we demonstrate that signal lines in SRAM arrays are prone to electromigration (EM). Our analysis shows that the read operation can cause unidirectional current flow in bit-lines. Thus the length of bit-lines should be bounded not only by performance requirements, but also by the Blech length constraint to avoid EM. We propose a method of determining the bit-line width under layout constraints to maximize the number of cells attached to a bit-line, while ensuing the reliability of the bit-line and maintaining SRAM performance. We also study the effects of SRAM parameter variations on the EM-safe bit-line length. Simulation results show that the EM-safe bit-line length decreases as technology scales, temperature or frequency rise, and parameter variations increase.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115034795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Fast FPGA-based fault injection tool for embedded processors 基于fpga的嵌入式处理器快速故障注入工具
International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523654
Mohammad Shokrolah Shirazi, B. Morris, H. Selvaraj
{"title":"Fast FPGA-based fault injection tool for embedded processors","authors":"Mohammad Shokrolah Shirazi, B. Morris, H. Selvaraj","doi":"10.1109/ISQED.2013.6523654","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523654","url":null,"abstract":"FPGA-based fault injection methods have recently become more popular since they provide high speed in fault injection experiments. During each fault injection experiment, FPGA should send data related with observation points back to host computer for fault tolerant analysis. Since there is high data volume, FPGA should spend most of its time in communication. In this paper, we solve this problem by bringing all parts of fault injection tool inside FPGA. The area overhead problem related with observation data is obviated by using simple observation circuit. As case study, we injected 6400 SEU faults into OpensRISC 1200 processor over the Cyclone II FPGA. Results show that our fault injection experiments are done more than 400 times faster than one of the traditional FPGA based fault injection methods with only 5% area overhead.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"187 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114017982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
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