Performance entitlement by exploiting transistor's BTI recovery

The inherent problem in signal probability (α) prediction has limited the scope of exploiting the transistor's BTI recovery at circuit level. In this paper, we present a design-for-reliability (DFR) methodology for digital designs, BTI_Refresh, that instead of relying on predicting α, sets it to a known value (~0.5) such that the BTI stress effects are alleviated and a predicted recovery effect could be guaranteed at circuit level. The technique can be applied equally to both NBTI and PBTI. Experimental results using Cadence Relxpert on critical paths extracted from industry designs show that with a negligible power, area overhead, a significant improvement (50%) in the total degradation of critical path performance with respect to end-of-life models is achievable.