International Symposium on Quality Electronic Design (ISQED)最新文献_第5页

Device design and analysis of logic circuits and SRAMs for Germanium FinFETs on SOI and bulk substrates 基于SOI和块状衬底的锗finfet逻辑电路和sram的器件设计与分析

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523633

V. Hu, M. Fan, P. Su, C. Chuang

引用次数: 2

An efficient method for ECSM characterization of CMOS inverter in nanometer range technologies 一种纳米范围内CMOS逆变器ECSM表征的有效方法

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523681

B. Kaur, S. Miryala, S. Manhas, B. Anand

{"title":"An efficient method for ECSM characterization of CMOS inverter in nanometer range technologies","authors":"B. Kaur, S. Miryala, S. Manhas, B. Anand","doi":"10.1109/ISQED.2013.6523681","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523681","url":null,"abstract":"Accurate estimation of delay is a major challenge in current nanometer regime using Non Linear Delay Model (NLDM) due to issues such as parametric variation, nonlinear capacitance value etc. It demands a large number of simulations to be performed for getting the accurate delay values. To partly solve this issue, people have started using Effective Current Source Model (ECSM), which stores certain predefined Threshold Crossing Point (TCP) of the output voltage waveform with respect to different input transition time (TR) values and load capacitance (Cl). In this work, we propose an analytical timing model relating 10% - 90% TCPs with Cl and TR values. We also derive the relationship between the cell size and the model coefficients. We also derive the region of validity of the model in (TR, Cl) space and determine its relationship with cell size. The proposed model is in good agreement with HSPICE simulations with a maximum relative error of 2.5%. We verified the proposed model with technology scaling. We use this model and the relationships to reduce the number of simulations in ECSM library characterization.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129094789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

On a rewriting strategy for dynamically managing power constraints and power dissipation in SoCs 一种动态管理soc中功率约束与功耗的重写策略

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523600

V. Viswanath, R. Muralidhar, Harinarayanan Seshadri, J. Abraham

{"title":"On a rewriting strategy for dynamically managing power constraints and power dissipation in SoCs","authors":"V. Viswanath, R. Muralidhar, Harinarayanan Seshadri, J. Abraham","doi":"10.1109/ISQED.2013.6523600","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523600","url":null,"abstract":"We present a novel and highly automated technique for dynamic system level power management of System-on-a-Chip (SoC) designs. We present a formal system to represent power constraints and power intent as rules. We also present a Term Rewriting Systems based rule rewriting engine as our dynamic power manager. We provide a notion of formal correctness of our rule engine execution and provide a robust algorithm to dynamically and automatically manage power consumption in large SoC designs. There are two fundamental building blocks at the core of our technique. First, we present a powerful formal system to capture power constraints and power intent as rules. This is a self-checking system and will automatically flag conflicting constraints or rules. Next, we present a rewriting strategy for managing power constraint rules using a formal deductive logic technique specially honed for dynamic power management of SoC designs. Together, this provides a common platform and representation to seamlessly cooperate between hardware and software constraints to achieve maximum platform power optimization dynamically during execution. We demonstrate our technique in multiple contexts on an SoC design of the state-of-the-art next generation Intel smartphone platform.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129228815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A novel flow for reducing clock skew considering NBTI effect and process variations 一种考虑NBTI效应和工艺变化的减小时钟偏差的新流程

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523630

Jifeng Chen, M. Tehranipoor

{"title":"A novel flow for reducing clock skew considering NBTI effect and process variations","authors":"Jifeng Chen, M. Tehranipoor","doi":"10.1109/ISQED.2013.6523630","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523630","url":null,"abstract":"Negative bias temperature instability (NBTI) has emerged as a major concern not only to the functional circuits, but also to the clock tree. Further aggravated by process variations, aging-induced reliability issue becomes more challenging when technology further scales. Development of effective solutions for reducing clock skew and compensating aging effect under process variations remains as a challenge. Taking the impact from NBTI and process variations into account, we propose a novel flow for reducing clock skew by selectively replacing standard-Vth clock buffers with their high-Vth counterparts. An extended “divide and conquer” algorithm is developed to identify the critical clock buffers for replacement. The area overhead of our proposed flow is negligible, and the power consumption is reduced as well. Simulation results show that the proposed flow can effectively reduce the clock skew by at least 20% by replacing only 1.08% clock buffers on average for 10 years of degradation, even under an extremely constrained condition. The efficiency of our flow will be higher when the clock tree structure has a higher depth, rendering it more favorable for large-scale industry designs.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"23 7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122444368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

A low power detection routing method for bufferless NoC 无缓冲NoC的低功耗检测路由方法

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523636

C. Hsu, K. Tsai, Jing-Fu Jheng, S. Ruan, Chung-An Shen

引用次数: 10

Min-cut based leakage power aware scheduling in high-level synthesis 基于最小截点的高阶综合漏功率感知调度

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523605

Nan Wang, Song Chen, T. Yoshimura

引用次数: 7

Multi-objective optimization algorithm for efficient pin-constrained droplet routing technique in digital microfluidic biochip 数字微流控生物芯片中高效管脚约束液滴路径技术的多目标优化算法

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523618

Soumyajit Chatterjee, H. Rahaman, T. Samanta

{"title":"Multi-objective optimization algorithm for efficient pin-constrained droplet routing technique in digital microfluidic biochip","authors":"Soumyajit Chatterjee, H. Rahaman, T. Samanta","doi":"10.1109/ISQED.2013.6523618","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523618","url":null,"abstract":"Design automation for digital microfluidic biochip comprises of many combinatorial optimization problems, which are NP-complete in nature. Efficient optimization algorithms to solve them is in dearth till date. In this paper, we propose a multi-objective optimization algorithm that simultaneously minimizes several resources during bioassay operations in a digital microfluidic biochip. We design the progressive droplet routing as a constrained multi-objective optimization problem considering three objective functions to be optimized, named (i) electrode usages, (ii) routing completion time, or latest arrival time, and (iii) control pin allocation. A composite objective function is constructed by a weighted sum of the first two objective functions. This composite function is minimized pertaining to an upper bound on the third objective function, control pin allocation. A fractional constant weight factor (λ) is chosen to confer upon the necessary weightage on the two factors involved in the composite objective function for accurate optimization procedure. We perform experimentations with several existing benchmarks, and experimental results are quite encouraging.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124475204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Compiler-assisted leakage energy optimization of media applications on stream architectures 流架构媒体应用的编译器辅助泄漏能量优化

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523599

Shan Cao, Zhaolin Li, Z. Chen, Guoyue Jiang, Shaojun Wei

引用次数: 0

Efficient translation validation of high-level synthesis 高级合成的高效翻译验证

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523660

Tun Li, Yang Guo, Wanwei Liu, Chiyuan Ma

{"title":"Efficient translation validation of high-level synthesis","authors":"Tun Li, Yang Guo, Wanwei Liu, Chiyuan Ma","doi":"10.1109/ISQED.2013.6523660","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523660","url":null,"abstract":"The growing design-productivity gap has made designers shift toward using high-level synthesis (HLS) techniques to generate register transfer level design from high-level languages like C/C++. Unfortunately, this translation process is very complex and is prone to introduce bug into the generated design, which can create a mismatch between what a designer intends and what is actually implemented in the circuit. In this paper, we present an efficient approach to validate the result of HLS against the initial high-level program using translation validation techniques. We redefined the bisimulation relation and proposed a novel algorithm based on it. When compared with the existing method, the proposed method can dramatically reduce the number of automated theorem prover (ATP) querying, which will in turn improve the time cost in equivalence validation. Our method is suitable for structure-preserving transformations such as carried out by Spark synthesizer. We have implemented our validating technique and compared it with a state-of-the-art translation validation method of HLS. The promising results show the effectiveness and efficiency of our method.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126368962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

A comparator energy model considering shallow trench isolation stress by geometric programming 通过几何编程考虑浅沟隔离应力的比较器能量模型

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523670

Gong Chen, Yu Zhang, Bo Yang, Qing Dong, S. Nakatake

引用次数: 3