A low power detection routing method for bufferless NoC

Abstract

Network-on-Chip has been proposed for high performance on-chip communication. The major component of a Network-on-Chip architecture is the router, which affects the data transmission latency, chip area and power consumption. Inside the router, buffers occupy a significant a mount of power and a large partition of chip area. Therefore bufferless NoC, which discards the buffers in the routers, has been proposed for solving the power and area problem. In this paper, a low power deflection routing method is proposed for the bufferless on-chip network dealing with the routing problem and achieving the low power goal. The proposed method uses routing matrix for constructing the possible routing path, and then selects the best route for each data packet. Only few calculations are used in this method therefore lowering power consumption the low power goal. The experimental result shows that the proposed approach can greatly reduce power consumption and chip are compared with previous work.