International Symposium on Quality Electronic Design (ISQED)最新文献_第10页

On the selection of adder unit in energy efficient vector processing 论高效矢量处理中加法器的选择

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523602

Ivan Ratković, Oscar Palomar, Milan Stanic, O. Unsal, A. Cristal, M. Valero

{"title":"On the selection of adder unit in energy efficient vector processing","authors":"Ivan Ratković, Oscar Palomar, Milan Stanic, O. Unsal, A. Cristal, M. Valero","doi":"10.1109/ISQED.2013.6523602","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523602","url":null,"abstract":"Vector processors are a very promising solution for mobile devices and servers due to their inherently energy-efficient way of exploiting data-level parallelism. Previous research on vector architectures predominantly focused on performance, so vector processors require a new design space exploration to achieve low power. In this paper, we present a design space exploration of adder unit for vector processors (VA), as it is one of the crucial components in the core design with a non-negligible impact in overall performance and power. For this interrelated circuit-architecture exploration, we developed a novel framework with both architectural- and circuit-level tools. Our framework includes both design- (e.g. adder's family type) and vector architecture-related parameters (e.g. vector length). Finally, we present guidelines on the selection of the most appropriate VA for different types of vector processors according to different sets of metrics of interest. For example, we found that 2-lane configurations are more EDP (Energy×Delay)-efficient than single lane configurations for low-end mobile processors.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132502680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

A system-level solution for managing spatial temperature gradients in thinned 3D ICs 一种系统级解决方案，用于管理薄化3D集成电路中的空间温度梯度

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523595

A. Annamalai, Raghavan Kumar, Arunkumar Vijayakumar, S. Kundu

{"title":"A system-level solution for managing spatial temperature gradients in thinned 3D ICs","authors":"A. Annamalai, Raghavan Kumar, Arunkumar Vijayakumar, S. Kundu","doi":"10.1109/ISQED.2013.6523595","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523595","url":null,"abstract":"As conventional CMOS technology is approaching scaling limits, the shift in trend towards stacked 3D Integrated Circuits (3D IC) is gaining more importance. 3D ICs offer reduced power dissipation, higher integration density, heterogeneous stacking and reduced interconnect delays. In a 3D IC stack, all but the bottom tier are thinned down to enable through-silicon vias (TSV). However, the thinning of the substrate increases the lateral thermal resistance resulting in higher intra-layer temperature gradients potentially leading to performance degradation and even functional errors. In this work, we study the effect of thinning the substrate on temperature profile of various tiers in 3D ICs. Our simulation results show that the intra-layer temperature gradient can be as high as 57°C. Often, the conventional static solutions lead to highly inefficient design. To this end, we present a system-level situation-aware integrated scheme that performs opportunistic thread migration and dynamic voltage and frequency scaling (DVFS) to effectively manage thermal violations while increasing the system throughput relative to stand-alone schemes.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133499365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

On the interactions between real-time scheduling and inter-thread cached interferences for multicore processors 多核处理器实时调度与线程间缓存干扰的交互研究

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523676

Yiqiang Ding, Wei Zhang

引用次数: 0

Enabling sizing for enhancing the static noise margins 启用大小以增强静态噪声边界

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523623

Valeriu Beiu, A. Beg, W. Ibrahim, F. Kharbash, M. Alioto

引用次数: 16

Energy-aware coarse-grained reconfigurable architectures using dynamically reconfigurable isolation cells 使用动态可重构隔离单元的能量感知的粗粒度可重构架构

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523597

Syed M. A. H. Jafri, Ozan Bag, A. Hemani, Nasim Farahini, K. Paul, J. Plosila, H. Tenhunen

{"title":"Energy-aware coarse-grained reconfigurable architectures using dynamically reconfigurable isolation cells","authors":"Syed M. A. H. Jafri, Ozan Bag, A. Hemani, Nasim Farahini, K. Paul, J. Plosila, H. Tenhunen","doi":"10.1109/ISQED.2013.6523597","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523597","url":null,"abstract":"This paper presents a self adaptive architecture to enhance the energy efficiency of coarse-grained reconfigurable architectures (CGRAs). Today, platforms host multiple applications, with arbitrary inter-application communication and concurrency patterns. Each application itself can have multiple versions (implementations with different degree of parallelism) and the optimal version can only be determined at runtime. For such scenarios, traditional worst case designs and compile time mapping decisions are neither optimal nor desirable. Existing solutions to this problem employ costly dedicated hardware to configure the operating point at runtime (using DVFS). As an alternative to dedicated hardware, we propose exploiting the reconfiguration features of modern CGRAs. Our solution relies on dynamically reconfigurable isolation cells (DRICs) and autonomous parallelism, voltage, and frequency selection algorithm (APVFS). The DRICs reduce the overheads of DVFS circuitry by configuring the existing resources as isolation cells. APVFS ensures high efficiency by dynamically selecting the parallelism, voltage and frequency trio, which consumes minimum power to meet the deadlines on available resources. Simulation results using representative applications (Matrix multiplication, FIR, and FFT) showed up to 23% and 51% reduction in power and energy, respectively, compared to traditional DVFS designs. Synthesis results have confirmed significant reduction in area overheads compared to state of the art DVFS methods.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117310185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 23

Effective thermal control techniques for liquid-cooled 3D multi-core processors 液冷3D多核处理器的有效热控制技术

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523583

Yue Hu, Shaoming Chen, Lu Peng, Edward Song, Jin-Woo Choi

引用次数: 6

Energy-efficient Spin-Transfer Torque RAM cache exploiting additional all-zero-data flags 节能自旋转移扭矩RAM缓存利用额外的全零数据标志

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523613

Jinwook Jung, Y. Nakata, M. Yoshimoto, H. Kawaguchi

{"title":"Energy-efficient Spin-Transfer Torque RAM cache exploiting additional all-zero-data flags","authors":"Jinwook Jung, Y. Nakata, M. Yoshimoto, H. Kawaguchi","doi":"10.1109/ISQED.2013.6523613","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523613","url":null,"abstract":"Large on-chip caches account for a considerable fraction of the total energy consumption in modern microprocessors. In this context, emerging Spin-Transfer Torque RAM (STT-RAM) has been regarded as a promising candidate to replace large on-chip SRAM caches in virtue of its nature of the zero leakage. However, large energy requirement of STT-RAM on write operations, resulting in a huge amount of dynamic energy consumption, precludes it from application to on-chip cache designs. In order to reduce the write energy of the STT-RAM cache thereby the total energy consumption, this paper provides an architectural technique which exploits the fact that many applications process a large number of zero data. The proposed design appends additional flags in cache tag arrays and set these additional bits if the corresponding data in the cache line is the zero-valued data in which all data bits are zero. Our experimental results show that the proposed cache design can reduce 73.78% and 69.30% of the dynamic energy on write operations at the byte and word granularities, respectively; total energy consumption reduced by 36.18% and 42.51%, respectively. In addition to the energy reduction, performance evaluation results indicate that the proposed cache improves the processor performance by 5.44% on average.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116142411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 24

Hybrid CMOS-TFET based register files for energy-efficient GPGPUs 基于CMOS-TFET的高效节能gpgpu寄存器文件

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523598

Zhi Li, Jingweijia Tan, Xin Fu

{"title":"Hybrid CMOS-TFET based register files for energy-efficient GPGPUs","authors":"Zhi Li, Jingweijia Tan, Xin Fu","doi":"10.1109/ISQED.2013.6523598","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523598","url":null,"abstract":"State-of-the-art General-Purpose computing on Graphics Processing Unit (GPGPU) is facing severe power challenge due to the increasing number of cores placed on a chip with decreasing feature size. In order to hide the long latency operations, GPGPU employs the fine-grained multi-threading among numerous active threads, leading to the sizeable register files with massive power consumption. Exploring the optimal power savings in register files becomes the critical and first step towards the energy-efficient GPGPUs. The conventional method to reduce dynamic power consumption is the supply voltage scaling, and the inter-bank tunneling FETs (TFETs) are the promising candidates compared to CMOS for low voltage operations regarding to both leakage and performance. However, always executing at the low voltage (so that low frequency) will result in significant performance degradation. In this study, we propose the hybrid CMOS-TFET based register files. To optimize the register power consumption, we allocate TFET-based registers to threads whose execution progress can be delayed to some degree to avoid the memory contentions with other threads, and the CMOS-based registers are still used for threads requiring normal execution speed. Our experimental results show that the proposed technique achieves 30% energy (including both dynamic and leakage) reduction in register files with little performance degradation compared to the baseline case equipped with naive power optimization technique.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116194480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Power Integrity analysis and discrete optimization of decoupling capacitors on high speed power planes by particle swarm optimization 基于粒子群算法的高速功率平面解耦电容器功率完整性分析及离散优化

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523682

J. N. Tripathi, R. Nagpal, N. Chhabra, Rakesh Malik, J. Mukherjee, P. Apte

引用次数: 5

Hierarchical dynamic power management using model-free reinforcement learning 使用无模型强化学习的分层动态电源管理

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523606

Yanzhi Wang, Maryam Triki, X. Lin, A. Ammari, Massoud Pedram

{"title":"Hierarchical dynamic power management using model-free reinforcement learning","authors":"Yanzhi Wang, Maryam Triki, X. Lin, A. Ammari, Massoud Pedram","doi":"10.1109/ISQED.2013.6523606","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523606","url":null,"abstract":"Model-free reinforcement learning (RL) has become a promising technique for designing a robust dynamic power management (DPM) framework that can cope with variations and uncertainties that emanate from hardware and application characteristics. Moreover, the potentially significant benefit of performing application-level scheduling as part of the system-level power management should be harnessed. This paper presents an architecture for hierarchical DPM in an embedded system composed of a processor chip and connected I/O devices (which are called system components.) The goal is to facilitate saving in the system component power consumption, which tends to dominate the total power consumption. The proposed (online) adaptive DPM technique consists of two layers: an RL-based component-level local power manager (LPM) and a system-level global power manager (GPM). The LPM performs component power and latency optimization. It employs temporal difference learning on semi-Markov decision process (SMDP) for model-free RL, and it is specifically optimized for an environment in which multiple (heterogeneous) types of applications can run in the embedded system. The GPM interacts with the CPU scheduler to perform effective application-level scheduling, thereby, enabling the LPM to do even more component power optimizations. In this hierarchical DPM framework, power and latency tradeoffs of each type of application can be precisely controlled based on a user-defined parameter. Experiments show that the amount of average power saving is up to 31.1% compared to existing approaches.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131556922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9