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[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic最新文献

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Parallel hardware algorithms with redundant number representations for multiple-valued arithmetic VLSI 多值算术VLSI中冗余数字表示的并行硬件算法
[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic Pub Date : 1992-05-27 DOI: 10.1109/ISMVL.1992.186815
S. Kawahito, Y. Mitsui, M. Ishida, Tetsuro Nakamura
{"title":"Parallel hardware algorithms with redundant number representations for multiple-valued arithmetic VLSI","authors":"S. Kawahito, Y. Mitsui, M. Ishida, Tetsuro Nakamura","doi":"10.1109/ISMVL.1992.186815","DOIUrl":"https://doi.org/10.1109/ISMVL.1992.186815","url":null,"abstract":"High-speed arithmetic algorithms based on redundant number representations with the digit set (0,1,2) in radix 2 are presented. The algorithms are suitable for implementing high-speed compact arithmetic in VLSI with multivalued logic circuits. Addition and subtraction can be performed in a constant time independent of the operand length. Internal n-digit multiplication and division using the redundant number representations can be performed in a time proportional to log/sub 2/ n and n, respectively. The circuits offer higher speed and greater compactness compared with the signed-digit arithmetic, since the basic addition cell has simpler scheme. The addition cell also has sufficient immunity to the supply voltage fluctuation and relatively low power dissipation.<<ETX>>","PeriodicalId":127091,"journal":{"name":"[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123909999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Semirigid sets of central relations over a finite domain 有限域上中心关系的半刚性集
[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic Pub Date : 1992-05-27 DOI: 10.1109/ISMVL.1992.186809
M. Miyakawa, A. Nozaki, Grant R. Pogosyan, I. Rosenberg
{"title":"Semirigid sets of central relations over a finite domain","authors":"M. Miyakawa, A. Nozaki, Grant R. Pogosyan, I. Rosenberg","doi":"10.1109/ISMVL.1992.186809","DOIUrl":"https://doi.org/10.1109/ISMVL.1992.186809","url":null,"abstract":"A set of central h-ary relations on a set A is called semirigid if the clones of k-valued logic functions determined by the relations share only the clone K/sub h-1/ consisting of all projections and all functions assuming at most h-1 values (12; K/sub 1/ is the set of trivial functions, i.e., the clone consisting of all constants and all projections). The problem of determining semirigid sets of central relations is studied. For the set of h-ary central relations with the centers of the largest size, it is shown that the set consisting of all such relations is the only semirigid set. It is also shown that the minimum size of a semirigid set of central h-ary relations is h+1. For k=4, semirigid sets of binary central relations are investigated in detail.<<ETX>>","PeriodicalId":127091,"journal":{"name":"[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123937784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Fault analysis on two-level (K+1)-valued logic circuits 二电平(K+1)值逻辑电路的故障分析
[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic Pub Date : 1992-05-27 DOI: 10.1109/ISMVL.1992.186793
Hui Min Wang, Chung-Len Lee, Jwu-E Chen
{"title":"Fault analysis on two-level (K+1)-valued logic circuits","authors":"Hui Min Wang, Chung-Len Lee, Jwu-E Chen","doi":"10.1109/ISMVL.1992.186793","DOIUrl":"https://doi.org/10.1109/ISMVL.1992.186793","url":null,"abstract":"A general form and a set of basic gates in implementing two-level (K+1)-valued logic circuits are presented. A complete fault analysis on the proposed circuit shows that all fanout stem faults can be collapsed to branch faults. A procedure is derived, based on the fault relationships obtained for fault collapsing. Results show that for a two-level (K+1)-valued logic circuit, faults can be reduced to 19% of the original total faults.<<ETX>>","PeriodicalId":127091,"journal":{"name":"[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116273311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A universal logic machine 通用逻辑机
[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic Pub Date : 1992-05-27 DOI: 10.1109/ISMVL.1992.186805
M. Perkowski
{"title":"A universal logic machine","authors":"M. Perkowski","doi":"10.1109/ISMVL.1992.186805","DOIUrl":"https://doi.org/10.1109/ISMVL.1992.186805","url":null,"abstract":"After a brief review of the history of logic machines, a description is given of the Cube Calculus Machine (CCM2). This machine is based on an architecture in which the data path has been designed to execute operations to cube calculus, an algebraic model popularly used to process and minimize Boolean functions. CCM2 realizes efficiently all cube calculus operations such as sharp and consensus. The positional cube representation used by CCM2 can also represent multivalued-input, binary-output cube calculus (MVCC) operands. CCM2 can also work with generalized MVCC, which was developed as an extension of MVCC. This extension allows the machine to operate on set logic, associative tuples, several multivalued input multivalued output logics, multioutput relations, and symbolic relations.<<ETX>>","PeriodicalId":127091,"journal":{"name":"[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114887594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Design of a 4-valued digital multiplier using an artificial heterogeneous two-layered neural network 基于人工异构双层神经网络的四值数字乘法器设计
[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic Pub Date : 1992-05-27 DOI: 10.1109/ISMVL.1992.186781
Chia-Lun J. Hu
{"title":"Design of a 4-valued digital multiplier using an artificial heterogeneous two-layered neural network","authors":"Chia-Lun J. Hu","doi":"10.1109/ISMVL.1992.186781","DOIUrl":"https://doi.org/10.1109/ISMVL.1992.186781","url":null,"abstract":"A two-layered parallel cascaded neural network using heterogeneous binary and ternary artificial neurons is used to implement the four-valued digital multiplication process. The hardware design is derived from a general M-valued perceptron mapping theory. It requires only three binary neurons and one ternary neuron. The use of heterogeneous perceptron mapping techniques allows the design to be reasonably simple and accurate.<<ETX>>","PeriodicalId":127091,"journal":{"name":"[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic","volume":"248 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125600230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Easily testable multiple-valued cellular arrays 易于测试的多值蜂窝阵列
[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic Pub Date : 1992-05-27 DOI: 10.1109/ISMVL.1992.186775
N. Kamiura, Y. Hata, F. Miyawaki, K. Yamato
{"title":"Easily testable multiple-valued cellular arrays","authors":"N. Kamiura, Y. Hata, F. Miyawaki, K. Yamato","doi":"10.1109/ISMVL.1992.186775","DOIUrl":"https://doi.org/10.1109/ISMVL.1992.186775","url":null,"abstract":"An easily testable k-valued cellular array consisting of input arrays and a control array that requires fewer cells than other methods is proposed. Stuck-at, open, and AND bridging faults are treated under the assumption that a single fault occurs in the array. Test input vectors can be easily generated from control inputs that specify the switches of cells. It is shown that a faulty cell can be effectively diagnosed by using several observable terminals and (k+1)-valued logic values.<<ETX>>","PeriodicalId":127091,"journal":{"name":"[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123767810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A deductive neural-logic system 演绎的神经逻辑系统
[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic Pub Date : 1992-05-27 DOI: 10.1109/ISMVL.1992.186783
Joo-Hwee Lim, H. Lui, H. Teh
{"title":"A deductive neural-logic system","authors":"Joo-Hwee Lim, H. Lui, H. Teh","doi":"10.1109/ISMVL.1992.186783","DOIUrl":"https://doi.org/10.1109/ISMVL.1992.186783","url":null,"abstract":"A propositional logic deductive system based on a three-valued neural-logic network model that the authors proposed earlier is described. It is shown that neural logic enriches the classical Boolean logic, and a heuristic search with pruning and an adaptive search are proposed as the control strategies. A system prototype and its practicality are discussed.<<ETX>>","PeriodicalId":127091,"journal":{"name":"[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115069290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
On the synthesis of MVL functions for current-mode CMOS circuits implementation 关于MVL函数的综合，用于电流型CMOS电路的实现
[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic Pub Date : 1992-05-27 DOI: 10.1109/ISMVL.1992.186799
M. Abd-El-Barr, M. I. Mahroos
{"title":"On the synthesis of MVL functions for current-mode CMOS circuits implementation","authors":"M. Abd-El-Barr, M. I. Mahroos","doi":"10.1109/ISMVL.1992.186799","DOIUrl":"https://doi.org/10.1109/ISMVL.1992.186799","url":null,"abstract":"Four-valued, one-variable multivalued logic (MVL) functions are synthesized using current-mode CMOS logic (CMCL) circuits. Use is made of the fact that in CMCL, addition of logic values (represented using discrete current values) can be performed at no cost and that negative logic values are readily available by reversing the direction of current flow. A synthesis procedure that is based on the cost-table approach is proposed. The procedure results in less expensive (in terms of the number of transistors needed) realizations than those achieved using existing techniques.<<ETX>>","PeriodicalId":127091,"journal":{"name":"[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic","volume":"511 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113998094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Aliasing in multiple-valued test data compaction 多值测试数据压缩中的混叠
[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic Pub Date : 1992-05-27 DOI: 10.1109/ISMVL.1992.186776
G. Edirisooriya, John P. Robinson
{"title":"Aliasing in multiple-valued test data compaction","authors":"G. Edirisooriya, John P. Robinson","doi":"10.1109/ISMVL.1992.186776","DOIUrl":"https://doi.org/10.1109/ISMVL.1992.186776","url":null,"abstract":"The possibility of using multivalued instead of binary linear multiple input shift registers (MISRs) for output compaction of multiple-valued logic circuits is discussed. The use of multivalued MISRs avoids the need for decoding the signals. A framework for examining aliasing in multiple-valued circular MISRs is presented. The exact aliasing probability is obtained for ternary and quaternary MISRs under an independent error model for an arbitrary test length. It is shown that multivalued MISRs perform better than their binary counterparts.<<ETX>>","PeriodicalId":127091,"journal":{"name":"[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic","volume":"29 19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116630974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Direct cover MVL minimization with cost-tables 直接覆盖最大起降点最小化与成本表
[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic Pub Date : 1992-05-27 DOI: 10.1109/ISMVL.1992.186778
G. Dueck
{"title":"Direct cover MVL minimization with cost-tables","authors":"G. Dueck","doi":"10.1109/ISMVL.1992.186778","DOIUrl":"https://doi.org/10.1109/ISMVL.1992.186778","url":null,"abstract":"A direct cover algorithm for minimizing multivalued logic functions is described. The use of cost tables facilitates cost efficient implementations. Current-mode CMOS circuits are considered as target implementations. However, the algorithm can be readily adapted to different technologies by making appropriate changes in the cost tables. Previous direct cover methods selected the most isolated minterm to be covered first. Empirical results show that it is advantageous to start with the most clustered minterm. The number of implicants which have to be considered to cover a selected minterm increases greatly when universal literals are used (as opposed to window literals). Therefore, it is essential to limit the entries in the cost tables. A novel link field, associated with each cost table entry, reduces the number of implicants considered to cover a selected minterm. Two metrics are used when choosing an implicant: cost efficiency and function complexity.<<ETX>>","PeriodicalId":127091,"journal":{"name":"[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132930836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
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