Fault analysis on two-level (K+1)-valued logic circuits

[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic Pub Date : 1992-05-27 DOI:10.1109/ISMVL.1992.186793

Hui Min Wang, Chung-Len Lee, Jwu-E Chen

引用次数: 1

Abstract

A general form and a set of basic gates in implementing two-level (K+1)-valued logic circuits are presented. A complete fault analysis on the proposed circuit shows that all fanout stem faults can be collapsed to branch faults. A procedure is derived, based on the fault relationships obtained for fault collapsing. Results show that for a two-level (K+1)-valued logic circuit, faults can be reduced to 19% of the original total faults.<>

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二电平(K+1)值逻辑电路的故障分析

给出了实现两电平(K+1)值逻辑电路的一般形式和一组基本门。对所提电路的完整故障分析表明，所有扇出杆故障都可以归结为支路故障。基于得到的故障关系，推导出了故障塌陷的过程。结果表明，对于两电平(K+1)值逻辑电路，故障可以减少到原总故障的19%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic

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