{"title":"基于人工异构双层神经网络的四值数字乘法器设计","authors":"Chia-Lun J. Hu","doi":"10.1109/ISMVL.1992.186781","DOIUrl":null,"url":null,"abstract":"A two-layered parallel cascaded neural network using heterogeneous binary and ternary artificial neurons is used to implement the four-valued digital multiplication process. The hardware design is derived from a general M-valued perceptron mapping theory. It requires only three binary neurons and one ternary neuron. The use of heterogeneous perceptron mapping techniques allows the design to be reasonably simple and accurate.<<ETX>>","PeriodicalId":127091,"journal":{"name":"[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic","volume":"248 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design of a 4-valued digital multiplier using an artificial heterogeneous two-layered neural network\",\"authors\":\"Chia-Lun J. Hu\",\"doi\":\"10.1109/ISMVL.1992.186781\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A two-layered parallel cascaded neural network using heterogeneous binary and ternary artificial neurons is used to implement the four-valued digital multiplication process. The hardware design is derived from a general M-valued perceptron mapping theory. It requires only three binary neurons and one ternary neuron. The use of heterogeneous perceptron mapping techniques allows the design to be reasonably simple and accurate.<<ETX>>\",\"PeriodicalId\":127091,\"journal\":{\"name\":\"[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic\",\"volume\":\"248 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-05-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISMVL.1992.186781\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISMVL.1992.186781","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of a 4-valued digital multiplier using an artificial heterogeneous two-layered neural network
A two-layered parallel cascaded neural network using heterogeneous binary and ternary artificial neurons is used to implement the four-valued digital multiplication process. The hardware design is derived from a general M-valued perceptron mapping theory. It requires only three binary neurons and one ternary neuron. The use of heterogeneous perceptron mapping techniques allows the design to be reasonably simple and accurate.<>