Parallel hardware algorithms with redundant number representations for multiple-valued arithmetic VLSI

Abstract

High-speed arithmetic algorithms based on redundant number representations with the digit set (0,1,2) in radix 2 are presented. The algorithms are suitable for implementing high-speed compact arithmetic in VLSI with multivalued logic circuits. Addition and subtraction can be performed in a constant time independent of the operand length. Internal n-digit multiplication and division using the redundant number representations can be performed in a time proportional to log/sub 2/ n and n, respectively. The circuits offer higher speed and greater compactness compared with the signed-digit arithmetic, since the basic addition cell has simpler scheme. The addition cell also has sufficient immunity to the supply voltage fluctuation and relatively low power dissipation.<>