Ankit Kaul, Yandong Luo, Xiaochen Peng, Shimeng Yu, M. Bakir
{"title":"Thermal Reliability Considerations of Resistive Synaptic Devices for 3D CIM System Performance","authors":"Ankit Kaul, Yandong Luo, Xiaochen Peng, Shimeng Yu, M. Bakir","doi":"10.1109/3dic52383.2021.9687612","DOIUrl":"https://doi.org/10.1109/3dic52383.2021.9687612","url":null,"abstract":"3D Heterogeneous integration (3D-HI) is a promising approach to stack a large amount of embedded memory required in state-of-the-art compute in-memory (CIM) AI accelerators. While embedded nonvolatile memory, such as resistive RAM (RRAM), is a promising alternative to SRAM/DRAM as a CIM synaptic device owing to high density, low leakage, and nondestructive read, thermal-induced conductance drift remains a challenge. Lower retention at higher temperatures can be more significant in dense memory-logic 3D integration due to increased volumetric power which has not been studied in prior work. The scope of this work is to quantify the thermal impact of different 3D-HI architectures on the reliability of 3D-integrated bipolar RRAM devices for CIM applications. We propose a device-system-application-level reliability evaluation methodology, using which 3D integration architectures and logic-memory partitioning configurations are benchmarked. The reduction in CIM inference accuracy at 10 years using conventional cooling was observed to be ≈53% for monolithic 3D compared to ≈10% for through-silicon via based 3D stacking. We demonstrate that long-term degradation in device retention and CIM inference accuracy can be mitigated with more efficient cooling architectures such as microfluidic cooling.","PeriodicalId":120750,"journal":{"name":"2021 IEEE International 3D Systems Integration Conference (3DIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130457653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Dubarry, L. Arnaud, M. Munoz, G. Mauguen, S. Moreau, R. Crochemore, N. Bresson, B. Aventurier
{"title":"3D interconnection using copper direct hybrid bonding for GaN on silicon wafer","authors":"C. Dubarry, L. Arnaud, M. Munoz, G. Mauguen, S. Moreau, R. Crochemore, N. Bresson, B. Aventurier","doi":"10.1109/3dic52383.2021.9687599","DOIUrl":"https://doi.org/10.1109/3dic52383.2021.9687599","url":null,"abstract":"3D integration of wafers stacking is obtained with a GaN-based wafer integrated on Si substrate and CMOS wafer. In this study, after planarization of the incoming wafers prior the bonding, wafer-to-wafer hybrid bonding technology was provided with a mirror design of Cu patterns embedded in silica matrix to provide direct 3D links in a face-to-face scheme with a low pitch of 3 $mumathrm{m}$. Then, 1 $mumathrm{m}$ Cu TSV-last patterned through the SOI substrate of the CMOS wafer with and AlCu routing lines was followed with copper pillars in order to connect the stack to the package. We present morphological and electrical characterizations of a test vehicle including a Cu/SiO2 hybrid bonding interface. Scanning Acoustic Microscopy, FIB-SEM and TEM cross-sections demonstrated both a perfect SiO2/SiO2 bonding as well as an excellent Cu/Cu connection validated with electrical data.","PeriodicalId":120750,"journal":{"name":"2021 IEEE International 3D Systems Integration Conference (3DIC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133398703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Numerical predictions of 3D power-supply on chip taking into considerations of proximity effect","authors":"Shinei Miyasaka, Satoshi Matumoto","doi":"10.1109/3dic52383.2021.9687606","DOIUrl":"https://doi.org/10.1109/3dic52383.2021.9687606","url":null,"abstract":"3D Power-SoC (Supply on Chip), which can ultimately miniaturize the power supply, is attracted attentions. It integrates Si-LSIs, power devices and passive elements on a single chip. 3D Power-SoC requires frequencies above 30MHz. In addition, it realizes a very high power density, however handling power is small because of miniaturization. Therefore, parallel connection is required to increase the power handing capacity. Therefore, it is necessary to consider the proximity effect of the spiral inductor when the power supplies connected in parallel. In this paper, we report the proximity effect of the inductor through simulations.","PeriodicalId":120750,"journal":{"name":"2021 IEEE International 3D Systems Integration Conference (3DIC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123676197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Fukushima, Shinichi Sakuyama, Masatomo Takahashi, H. Hashimoto, J. Bea, Theodorus Marcello, H. Kino, Tetsu Tanaka, M. Koyanagi, M. Murugesan
{"title":"Integration of Damage-less Probe Cards Using Nano-TSV Technology for Microbumped Wafer Testing","authors":"T. Fukushima, Shinichi Sakuyama, Masatomo Takahashi, H. Hashimoto, J. Bea, Theodorus Marcello, H. Kino, Tetsu Tanaka, M. Koyanagi, M. Murugesan","doi":"10.1109/3dic52383.2021.9687601","DOIUrl":"https://doi.org/10.1109/3dic52383.2021.9687601","url":null,"abstract":"This paper describes nano-scale probe integration on a printed circuit board (PCB) using electroless TSV formation technology for achieving small scrub marks when testing solder microbumps formed on LSI wafers. The nanoprobes are resulted from the backside grinding and dry etching of Si substrates in which an array of Ni/Cu-TSVs with a tip diameter of 500 nm are fabricated. The TSV nanoprobes are also transferred to the PCB before the Si etch step. We demonstrate the probe contact to a thin solder layer for testing wafer-level packages with fine-pitch microbumps. In addition, the nanoprobes are electrically and mechanically characterized in this study.","PeriodicalId":120750,"journal":{"name":"2021 IEEE International 3D Systems Integration Conference (3DIC)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125307651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Review of 3D-Dynamic Random-Access Memory based Near-Memory Computation","authors":"P. P. Ravichandiran, P. Franzon","doi":"10.1109/3dic52383.2021.9687615","DOIUrl":"https://doi.org/10.1109/3dic52383.2021.9687615","url":null,"abstract":"The growth of Neural Networks (NNs) and Machine Learning (ML) usage has rapidly increased over the last decade. Traditional dynamic random-access memory (DRAM) is struggling to meet the computational, throughput demands of these NNs and has become a bottleneck in the system. One of the commonly proposed solutions is Near-Memory Computation (NMC) hardware accelerators to move the computation closer to the data resulting in improved throughput and reduced power consumption. In this paper, we analyze a few critical NMC architecture implementations, specifically those with 3D-Stacked DRAM memory. We have organized a literature review across structures, configuration, application, performance metrics, and present challenges and opportunities.","PeriodicalId":120750,"journal":{"name":"2021 IEEE International 3D Systems Integration Conference (3DIC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122719034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"[Copyright notice]","authors":"","doi":"10.1109/3dic52383.2021.9687616","DOIUrl":"https://doi.org/10.1109/3dic52383.2021.9687616","url":null,"abstract":"","PeriodicalId":120750,"journal":{"name":"2021 IEEE International 3D Systems Integration Conference (3DIC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126688107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"[Title page]","authors":"","doi":"10.1109/3dic52383.2021.9687619","DOIUrl":"https://doi.org/10.1109/3dic52383.2021.9687619","url":null,"abstract":"","PeriodicalId":120750,"journal":{"name":"2021 IEEE International 3D Systems Integration Conference (3DIC)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134539632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Numerical investigations for 3D power supply on chip by coupling of thermal-fluid, circuit, and electromagnetic field simulations","authors":"Ayano Furue, S. Matsumoto","doi":"10.1109/3dic52383.2021.9687610","DOIUrl":"https://doi.org/10.1109/3dic52383.2021.9687610","url":null,"abstract":"3D power supply on chip (3D power SoC), which integrates Si driver, GaN power device and passive devices realizes high efficiency at high frequency switching and high power density. However, miniaturization makes power supply high temperature, and it causes reduction in efficiency and lifetime of power supply. In this paper, we propose the optimum structure for stacking GaN power device and Si based IC circuit to 3D power SoC. We also discuss the optimum assembly technology through thermal-fluid, circuit, and electromagnetic field simulations.","PeriodicalId":120750,"journal":{"name":"2021 IEEE International 3D Systems Integration Conference (3DIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115389548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Liangxing Hu, S. Goh, Y. Lim, P. Zhao, Michael Joo Zhong Lim, C. S. Tan
{"title":"Multi-Die to Wafer Bonding Through Plasma-Activated Cu-Cu Direct Bonding in Ambient Conditions","authors":"Liangxing Hu, S. Goh, Y. Lim, P. Zhao, Michael Joo Zhong Lim, C. S. Tan","doi":"10.1109/3dic52383.2021.9687609","DOIUrl":"https://doi.org/10.1109/3dic52383.2021.9687609","url":null,"abstract":"In this work, we study multi-die to wafer bonding through plasma-activated Cu-Cu direct bonding carried out at room temperature in cleanroom ambient conditions. During the pre-bonding phase, surface analyses (e.g. surface profile, surface roughness, water contact angle and surface chemical states) are performed on both the as-deposited and the Ar/N2 plasma-activated Cu surfaces. It is found that the Ar/N2 plasma-activated Cu surface has lower water contact angle and surface roughness than the as-deposited Cu surface. From XPS, a thin passivation layer of CUxN is produced on the Ar/N2 plasma-activated Cu surface, which prevents the activated Cu from oxidation. The Ar/N2 plasma-activated dies are bonded onto a wafer at room temperature in ambient conditions and annealed at 300°C for 1 hour, where successful bonding is achieved. This bonding scheme shows promising features for high-throughput advanced 3D packaging and heterogeneous integration.","PeriodicalId":120750,"journal":{"name":"2021 IEEE International 3D Systems Integration Conference (3DIC)","volume":"2023 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121501153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Virtual Platform for Object Detection Systems","authors":"Qianli Zhao, W. R. Davis","doi":"10.1109/3dic52383.2021.9687602","DOIUrl":"https://doi.org/10.1109/3dic52383.2021.9687602","url":null,"abstract":"Computer vision is increasingly effective and important in many applications, including disease diagnosis, sports, and autonomous-driving. Visual recognition tasks, such as image classification and object detection, are the key of many of these applications, and recent developments in convolutional neural networks (CNNs) have made outstanding leaps in performance. Therefore, optimizing the data-flow between the image sensor and CNNs now constitute the majority of the effort in computer vision system design. System performance is sensitive to the qualities of the image sensor and CNN hardware accelerator. We focus on determining the influence of the sensor and accelerator on the overall performance and power of an object detection inference task. Because the relationship between image sensor quality and CNN performance is complex, we use image quality as a bridge when evaluating system performance. Developing a new product is very expensive and time consuming. This paper will offer an virtual platform for object detection systems, and each component in the system will be simulated by a proper power model and a behavior model. The power, performance, and area of the complete system will be predicted to help designers optimize object detection systems.","PeriodicalId":120750,"journal":{"name":"2021 IEEE International 3D Systems Integration Conference (3DIC)","volume":"43 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114043076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}