3D interconnection using copper direct hybrid bonding for GaN on silicon wafer

Abstract

3D integration of wafers stacking is obtained with a GaN-based wafer integrated on Si substrate and CMOS wafer. In this study, after planarization of the incoming wafers prior the bonding, wafer-to-wafer hybrid bonding technology was provided with a mirror design of Cu patterns embedded in silica matrix to provide direct 3D links in a face-to-face scheme with a low pitch of 3 $\mu\mathrm{m}$. Then, 1 $\mu\mathrm{m}$ Cu TSV-last patterned through the SOI substrate of the CMOS wafer with and AlCu routing lines was followed with copper pillars in order to connect the stack to the package. We present morphological and electrical characterizations of a test vehicle including a Cu/SiO2 hybrid bonding interface. Scanning Acoustic Microscopy, FIB-SEM and TEM cross-sections demonstrated both a perfect SiO2/SiO2 bonding as well as an excellent Cu/Cu connection validated with electrical data.