2021 IEEE International 3D Systems Integration Conference (3DIC)最新文献

{"title":"Cu-Cu Direct Bonding Through Highly Oriented Cu Grains for 3D-LSI Applications","authors":"M. Murugesan, E. Sone, A. Simomura, M. Motoyoshi, M. Sawa, K. Fukuda, M. Koyanagi, T. Fukushima","doi":"10.1109/3dic52383.2021.9687604","DOIUrl":"https://doi.org/10.1109/3dic52383.2021.9687604","url":null,"abstract":"The effect of an extremely large and relatively ordered Cu grains the yield of Cu-Cu direct bonding was investigated. Our modified electroplating process followed by post processing has resulted into the formation of 10–15 $mumathrm{m}$ large Cu grains before Cu-Cu direct bonding. The microstructural evaluation showed formation relatively (100) oriented Cu-grains. The less hard and strain-suppressed Cu-grains as inferred from respectively, Vickers hardness and tensile test highly facilitates the Cu diffusion across the oriented grains during the Cu-Cu direct/hybrid bonding.","PeriodicalId":120750,"journal":{"name":"2021 IEEE International 3D Systems Integration Conference (3DIC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124743884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Proposed Standardization of Heterogenous Integrated Chiplet Models","authors":"Anthony Mastroianni, Benjamin Kerr, J. Nasrullah, Kevin Cameron, Hockshan James Wong, David Ratchkov, J. Reynick","doi":"10.1109/3dic52383.2021.9687611","DOIUrl":"https://doi.org/10.1109/3dic52383.2021.9687611","url":null,"abstract":"With the economics of transistor scaling no longer universally applicable, the semiconductor industry faces an inflection point as higher cost, lower yield, and reticle size limitations drive the need for viable alternatives to traditional monolithic solutions. What we see is the move to innovative packaging technologies to support system-scaling demands and achieve lower system cost. This is driving an emerging trend to disaggregate what typically would be implemented as a single homogeneous, system-on-silicon (SOC) ASIC device into discrete, unpackaged ASIC devices, otherwise known as chiplets. These chiplets typically provide a specific function implemented in an optimal chip process node. Several of these chiplet devices are mounted and interconnected into a single package using high speed/bandwidth interfaces to deliver monolithic or greater performance at reduced cost, higher yield, and lower power with only a slightly larger area than a heterogeneous integrated advanced package. As fabless semiconductor companies begin to bring these disaggregated chiplets to market, their successful adoption requires the industry to standardize on a set of interface protocols in order to offer plug-and-play compatibility between different suppliers' chiplets, creating a true open ecosystem and supply chain. Integrating these multi-vendor chiplets into a heterogeneous package assembly will also require chiplet vendors to provide their customers with a standardized set of design model deliverables in order to ensure operability in the end users EDA tool design workflows. In this paper, we propose a set of standardized models that include thermal, physical, mechanical, IO, behavioral, power, signal and power integrity, electrical properties, and test models, as well as documentation to facilitate the integration of the chiplets into a design. Additionally, security traceability assurance is an emerging need to ensure trusted supply chain and operational security of the chiplets and the resulting packaged devices. It is strongly recommended that these models are electronically readable for use in the design work flows. The models should leverage available, existing industry standards, with extensions and/or new standards defined as necessary. The initial scope of these proposed models is currently targeted for 2.5D interposer-based designs. Note that these 2.5D structures may include silicon interposers, silicon bridges, or organic based fan-out/RDL packaging technologies, which can be referred to as “organic interposers.” Additional or modified deliverables will be required to address the needs of 3D designs.","PeriodicalId":120750,"journal":{"name":"2021 IEEE International 3D Systems Integration Conference (3DIC)","volume":"106 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114003428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Electrical and Performance Benefits of Advanced Monolithic Cooling for 2.5D Heterogeneous ICs","authors":"Sreejith Kochupurackal Rajan, Ankit Kaul, G. May, M. Bakir","doi":"10.1109/3dic52383.2021.9687618","DOIUrl":"https://doi.org/10.1109/3dic52383.2021.9687618","url":null,"abstract":"The rising prominence of heterogeneous integration, coupled with increase in device power, presents unique thermal challenges. Past work has demonstrated the benefits of mono-lithic microfluidic cooling for mitigating these in 2.5D ICs. In this paper, we evaluate the electrical performance benefits of this technology using finite element modeling and experimental demonstration on functional silicon. Ansys models show up to 23.3 × lower thermal coupling between the core chiplets in a CPU with microfluidic cooling compared to traditional air-cooled configurations. Finally, we demonstrate a micropin-fin heatsink etched on the backside of five chiplets in a 2.5D FPGA package and capped with 3D printed manifolds for fluid delivery. A 50.5 % increase in sustained power dissipation for similar die temperatures was achieved with the monolithic heatsink using a 52.5 °C DI water inlet, when compared to the stock cold-plate.","PeriodicalId":120750,"journal":{"name":"2021 IEEE International 3D Systems Integration Conference (3DIC)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127041788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design for 3-D Stacked Neural Network Circuit with Cyclic Analog Computing","authors":"K. Kiyoyama, Y. Horio, T. Fukushima, H. Hashimoto, Takemori Orima, M. Koyanagi","doi":"10.1109/3dic52383.2021.9687608","DOIUrl":"https://doi.org/10.1109/3dic52383.2021.9687608","url":null,"abstract":"An analog-based CMOS neuron with crossbar configuration multiplier-adder circuit for three-dimensional chip stacking (3-D) cyclic signal processing deep neural network is presented. The circuit designed to verify the proposed concept is a total of four-layer stacked chips, consisting of two neuron chips that mainly perform analog multiply-accumulate (MAC) operations and two memory chips that store neuron potential (activation) and weight data. According to papers and conference presentations on accelerators for the neural network circuit, the analog MAC operation has the potential to achieve high efficiency by using the analog processing of the crossbar configuration. However, analog MAC circuit with compensation technique is required to overcome the decrease in computing accuracy due to electrical noise and element nonlinearity. In this study, we have designed and verified a highly linearity multiplier-adder circuit for highly efficient 3-D cyclic analog processing. In this paper, we focus on the current adder circuit with switched capacitor correlated double sampling (CDS) technique, to minimize non-linearity, noise, and circuit area. The proposed the analog adder circuit was designed with 180-nm and operation power supply voltage 1.8V CMOS technology, and the fabricated neuron chip that integrates 64 neurons and $64 times 64$ synaptic connections. As analysis results, it was confirmed that the CDS technique apply analog adder circuit reduced the noise output voltage less than 0.1mV and the range of voltage linearity was over 1.6V.","PeriodicalId":120750,"journal":{"name":"2021 IEEE International 3D Systems Integration Conference (3DIC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133671106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Implementation of a Chaotic Neural Network Reservoir on a TSV/$mutext{Bump}$ Stacked 3D Cyclic Neural Network Integrated Circuit","authors":"Y. Horio, Takemori Orima, K. Kiyoyama, M. Koyanagi","doi":"10.1109/3dic52383.2021.9687614","DOIUrl":"https://doi.org/10.1109/3dic52383.2021.9687614","url":null,"abstract":"A TSV/$mutext{Bump}$ stacked 3D cyclic deep neural network integrated circuit architecture was proposed. Furthermore, a technique for embedding a chaotic neural network reservoir into the proposed architecture was devised. A proof-of-concept neural network chip, and a weight memory chip have been designed and fabricated to confirm the feasibly of the proposed architecture. In this study, the neuron chip configured as a cyclic chaotic neuron circuit is evaluated by measuring circuit building blocks, and constructing a dedicated MATLAB circuit emulator based on the measurement results from the chip. Some of the results from the MATLAB emulator are illustrated.","PeriodicalId":120750,"journal":{"name":"2021 IEEE International 3D Systems Integration Conference (3DIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125137351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fully integrated transformer less floating gate driver for 3D power supply on chip","authors":"Yuske Ogushi, S. Matsumoto","doi":"10.1109/3dic52383.2021.9687603","DOIUrl":"https://doi.org/10.1109/3dic52383.2021.9687603","url":null,"abstract":"Power supply on chip (power SoC) has been caught attentions because it can ultimately miniaturize the power supplies. To realize 3D power SoC which is fabricated using mass production process, we need to meet the various electrical requirements. Series and/or parallel connections is mentioned as good method. In such a situation, we previously proposed transformer less floating gate driver circuit using Schottky barrier diode (SBD). However, SBD is not suitable for integration. In this paper, we investigate the transformer less floating gate driver using MOS devices.","PeriodicalId":120750,"journal":{"name":"2021 IEEE International 3D Systems Integration Conference (3DIC)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115128938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Welcome to 3DIC 2021","authors":"","doi":"10.1109/3dic52383.2021.9687613","DOIUrl":"https://doi.org/10.1109/3dic52383.2021.9687613","url":null,"abstract":"","PeriodicalId":120750,"journal":{"name":"2021 IEEE International 3D Systems Integration Conference (3DIC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123963190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Low-Cost and Low-Temperature Method to Realize Carbon Nanotube Conductor in Through-Silicon-Via","authors":"Ziyue Zhang, Yingtao Ding, Baoyan Yang, Anrun Ren, Zhiming Chen","doi":"10.1109/3dic52383.2021.9687607","DOIUrl":"https://doi.org/10.1109/3dic52383.2021.9687607","url":null,"abstract":"Through-silicon-via (TSV) technology is the key to three-dimensional (3D) heterogeneous integration strategy. In this paper, a novel low-cost and low-temperature method to fabricate carbon nanotube (CNT) conductor in blind TSV is proposed. Based on a series of precise operations of the conductive water-based solution of metallic CNTs including coating, vacuum treatment, and spinning, dense CNTs are successfully filled into blind TSVs of various dimensions, which can serve as the TSV conductors. This method avoids the expensive and high-temperature processes to grow or transport CNT conductors in TSVs, and is compatible with other integration strategies. Moreover, together with the vacuum-assisted spin coating of polyimide (PI) liners, a low-cost and low-temperature fabrication flow for blind TSVs can be achieved. This work provides a promising method towards the fabrication and application of CNT based TSVs.","PeriodicalId":120750,"journal":{"name":"2021 IEEE International 3D Systems Integration Conference (3DIC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121644526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Bond Strength Optimization of Plasma Activated Low Temperature Oxide-Oxide Fusion Bonding Through Thermocycling","authors":"P. Krüger, T. Voß, M. Wietstruck","doi":"10.1109/3dic52383.2021.9687600","DOIUrl":"https://doi.org/10.1109/3dic52383.2021.9687600","url":null,"abstract":"In this work, the influence of annealing time and number of annealing steps on the shear strength of plasma activated low temperature oxide-oxide fusion bonding wafer stacks is investigated. Shear strength measurements of previously manufactured shear strength measurement test structures are introduced to analyze the shear strength and related bond strength, respectively. An improved two-step annealing/cooling thermocycle is demonstrated which leads to a tremendous increase of the shear strength compared to a conventional single annealing step. Based on an optimized annealing through thermocycling, plasma activated low temperature oxide-oxide fusion bonding with reduced process time, lower temperature and higher bond strength becomes feasible.","PeriodicalId":120750,"journal":{"name":"2021 IEEE International 3D Systems Integration Conference (3DIC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130634264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Multi-ANN embedded system based on a custom 3D-DRAM","authors":"Lee Baker, R. Patti, P. Franzon","doi":"10.1109/3dic52383.2021.9687617","DOIUrl":"https://doi.org/10.1109/3dic52383.2021.9687617","url":null,"abstract":"Machine Learning in the form of Artificial Neural Networks (ANNs) has gained considerable traction in applications such as image recognition and speech recognition. These applications typically employ a subset of ANNs known as Convolutional Neural Networks (CNNs) which re-use parameters and thus reduce main memory bandwidth. However, there are other types of ANN that do not provide reuse opportunities such as autoencoders and Long Short-term memory. Most research has focused on implementing CNNs but because of their extensive use of SRAM have both ANN size restrictions and performance degradation when used in applications that utilize other types of ANN. This work demon-strates how a customized 3D-DRAM with a very wide databus can be combined with application-specific layers to produce a system meeting the requirements of embedded systems employing multiple instances of disparate ANNs.","PeriodicalId":120750,"journal":{"name":"2021 IEEE International 3D Systems Integration Conference (3DIC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124030238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}