Proposed Standardization of Heterogenous Integrated Chiplet Models

Abstract

With the economics of transistor scaling no longer universally applicable, the semiconductor industry faces an inflection point as higher cost, lower yield, and reticle size limitations drive the need for viable alternatives to traditional monolithic solutions. What we see is the move to innovative packaging technologies to support system-scaling demands and achieve lower system cost. This is driving an emerging trend to disaggregate what typically would be implemented as a single homogeneous, system-on-silicon (SOC) ASIC device into discrete, unpackaged ASIC devices, otherwise known as chiplets. These chiplets typically provide a specific function implemented in an optimal chip process node. Several of these chiplet devices are mounted and interconnected into a single package using high speed/bandwidth interfaces to deliver monolithic or greater performance at reduced cost, higher yield, and lower power with only a slightly larger area than a heterogeneous integrated advanced package. As fabless semiconductor companies begin to bring these disaggregated chiplets to market, their successful adoption requires the industry to standardize on a set of interface protocols in order to offer plug-and-play compatibility between different suppliers' chiplets, creating a true open ecosystem and supply chain. Integrating these multi-vendor chiplets into a heterogeneous package assembly will also require chiplet vendors to provide their customers with a standardized set of design model deliverables in order to ensure operability in the end users EDA tool design workflows. In this paper, we propose a set of standardized models that include thermal, physical, mechanical, IO, behavioral, power, signal and power integrity, electrical properties, and test models, as well as documentation to facilitate the integration of the chiplets into a design. Additionally, security traceability assurance is an emerging need to ensure trusted supply chain and operational security of the chiplets and the resulting packaged devices. It is strongly recommended that these models are electronically readable for use in the design work flows. The models should leverage available, existing industry standards, with extensions and/or new standards defined as necessary. The initial scope of these proposed models is currently targeted for 2.5D interposer-based designs. Note that these 2.5D structures may include silicon interposers, silicon bridges, or organic based fan-out/RDL packaging technologies, which can be referred to as “organic interposers.” Additional or modified deliverables will be required to address the needs of 3D designs.