Implementation of a Chaotic Neural Network Reservoir on a TSV/$\mu\text{Bump}$ Stacked 3D Cyclic Neural Network Integrated Circuit

Abstract

A TSV/$\mu\text{Bump}$ stacked 3D cyclic deep neural network integrated circuit architecture was proposed. Furthermore, a technique for embedding a chaotic neural network reservoir into the proposed architecture was devised. A proof-of-concept neural network chip, and a weight memory chip have been designed and fabricated to confirm the feasibly of the proposed architecture. In this study, the neuron chip configured as a cyclic chaotic neuron circuit is evaluated by measuring circuit building blocks, and constructing a dedicated MATLAB circuit emulator based on the measurement results from the chip. Some of the results from the MATLAB emulator are illustrated.