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A 12GHz 22dB-gain-control SiGe bipolar VGA with 2° phase shift variation 具有2°相移变化的12GHz 22db增益控制SiGe双极VGA
ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC) Pub Date : 2015-11-02 DOI: 10.1109/ESSCIRC.2015.7313827
F. Padovan, M. Tiebout, A. Neviani, A. Bevilacqua
{"title":"A 12GHz 22dB-gain-control SiGe bipolar VGA with 2° phase shift variation","authors":"F. Padovan, M. Tiebout, A. Neviani, A. Bevilacqua","doi":"10.1109/ESSCIRC.2015.7313827","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313827","url":null,"abstract":"A 12GHz VGA is presented that shows a gain control from -9dB to 13dB in a linear-in-dB fashion. As the gain is changed, the phase shift over the entire 10 to 14.4 GHz bandwidth varies as little as ≤2° due to a compensation circuitry that reduces the input-output phase shift sensitivity to gain variations. The VGA prototypes, implemented in a SiGe bipolar technology, show a noise figure of 5.1 dB, an IIP3 of -3dBm, and a power consumption of 83mW.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90978453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An integrated fluxgate magnetometer for use in closed-loop/open-loop isolated current sensing 用于闭环/开环隔离电流传感的集成磁通门磁强计
ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC) Pub Date : 2015-11-02 DOI: 10.1109/ESSCIRC.2015.7313877
M. Snoeij, V. Schaffer, S. Udayashankar, Mikhail V. Ivanov
{"title":"An integrated fluxgate magnetometer for use in closed-loop/open-loop isolated current sensing","authors":"M. Snoeij, V. Schaffer, S. Udayashankar, Mikhail V. Ivanov","doi":"10.1109/ESSCIRC.2015.7313877","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313877","url":null,"abstract":"This paper presents two integrated magnetic sensor ICs for isolated current sensing. Both employ an integrated fluxgate magnetometer with a sensitivity of 250V/T and a 500ksps readout circuit. Only 5.4mW is required to excite the sensor, which is 20x more power efficient than the state-of-the-art. With an external magnetic core, the resulting closed-loop current sensor IC achieves a dynamic range of 112dB and a non-linearity below 0.03%, while the open-loop current sensor IC has a dynamic range of 100dB and a non-linearity below 0.2%.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87785145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
A wide tuning range 4 th-order Gm-C elliptic filter for wideband multi-standards GNSS receivers 用于宽带多标准GNSS接收机的宽调谐范围4阶Gm-C椭圆滤波器
ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC) Pub Date : 2015-11-02 DOI: 10.1109/ESSCIRC.2015.7313823
Saeed Ghamari, G. Tasselli, C. Botteron, P. Farine
{"title":"A wide tuning range 4 th-order Gm-C elliptic filter for wideband multi-standards GNSS receivers","authors":"Saeed Ghamari, G. Tasselli, C. Botteron, P. Farine","doi":"10.1109/ESSCIRC.2015.7313823","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313823","url":null,"abstract":"A 4 th order Gm-C elliptic low-pass filter with a wide continuous tuning range is presented. The continuous tuning is achieved by means of a new tuning circuit which adjusts the bias current of the Gm cell's input stage to control the cut-off frequency. With this tuning circuit, power efficiency is achieved by scaling down the power consumption proportionally to the cut-off frequency while keeping the linearity near constant over a wide range of frequencies. To extend the tuning range of the filter, Gm switching was employed which also acts on the Gm cell's input stage without adding any switches in the signal path. The filter was fabricated using UMC 180-nm CMOS technology on an active area of 0.23 mm2. Its cut-off frequency ranges continuously from 7.4 to 27.4 MHz. This wide range of possible tuning makes the filter suitable for modern wideband GNSS signals in zero-IF receivers. The filter consumes 2.1 and 7.5 mA (from 1.8 V) at its lowest and highest cut-off frequencies, respectively, and achieves a high input IP3 of up to -1.3 dBVRMS.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74517419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A BIST structure for the evaluation of the MOSFET gate dielectric interface state density in post-processed CMOS chips 一种用于评价后处理CMOS芯片中MOSFET栅极介电界面态密度的BIST结构
ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC) Pub Date : 2015-11-02 DOI: 10.1109/ESSCIRC.2015.7313915
N. Dodel, S. Keil, Andreas Wiemhofer, Malte Kortstock, P. Scholz, U. Kerst, R. Thewes
{"title":"A BIST structure for the evaluation of the MOSFET gate dielectric interface state density in post-processed CMOS chips","authors":"N. Dodel, S. Keil, Andreas Wiemhofer, Malte Kortstock, P. Scholz, U. Kerst, R. Thewes","doi":"10.1109/ESSCIRC.2015.7313915","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313915","url":null,"abstract":"A highly accurate built-in-self-test (BIST) structure is presented which reveals the gate dielectric interface state density of the MOS transistors of CMOS chips. A specific measurement setup or equipment is not required. The interface state density is directly A/D converted. The structure can be easily integrated into any chip with a standard digital interface.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78295293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 3.6pJ/b 56Gb/s 4-PAM receiver with 6-Bit TI-SAR ADC and quarter-rate speculative 2-tap DFE in 32 nm CMOS 一个3.6pJ/b 56Gb/s 4-PAM接收器，带有6位TI-SAR ADC和1 / 4速率投机2分导DFE，采用32nm CMOS
ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC) Pub Date : 2015-11-02 DOI: 10.1109/ESSCIRC.2015.7313850
Hazar Yueksel, L. Kull, A. Burg, M. Braendli, P. Buchmann, P. Francese, C. Menolfi, M. Kossel, T. Morf, T. Andersen, D. Luu, T. Toifl
{"title":"A 3.6pJ/b 56Gb/s 4-PAM receiver with 6-Bit TI-SAR ADC and quarter-rate speculative 2-tap DFE in 32 nm CMOS","authors":"Hazar Yueksel, L. Kull, A. Burg, M. Braendli, P. Buchmann, P. Francese, C. Menolfi, M. Kossel, T. Morf, T. Andersen, D. Luu, T. Toifl","doi":"10.1109/ESSCIRC.2015.7313850","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313850","url":null,"abstract":"This paper describes the implementation of a 4-level pulse-amplitude-modulation (4-PAM) receiver consisting of a 6-bit time-interleaved successive-approximation analog-to-digital converter (TI-SAR ADC), followed by a fully digital speculative 2-tap decision-feedback equalizer (DFE) operating at one-fourth of the modulation rate. The receiver, implemented in an experimental chip fabricated in 32 nm SOI CMOS, is designed to recover data at 56Gb/s over a channel with an attenuation of 11 dB at 14 GHz. The power consumption of the receiver is 202.7 mW at a supply of 1.2 V, achieving an overall energy efficiency of 3.62 pJ/b. The DFE along with area-optimized register arrays and memory-control buffers occupies an area of 0.154×0.169 mm2. Experimental results demonstrating a BER<;10-8 are obtained using a (27-1)-bit pseudo-random binary sequence (PRBS-7).","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78497021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
A 48mW 15-to-28Gb/s source-synchronous receiver with adaptive DFE using hybrid alternate clock scheme and baud-rate CDR in 65nm CMOS 采用混合备用时钟方案和65nm CMOS波特率CDR的48mW 15- 28gb /s源同步接收机
ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC) Pub Date : 2015-11-02 DOI: 10.1109/ESSCIRC.2015.7313849
S. Yuan, Liji Wu, Ziqiang Wang, Xuqiang Zheng, Peng Wang, Wen Jia, Chun Zhang, Zhihua Wang
{"title":"A 48mW 15-to-28Gb/s source-synchronous receiver with adaptive DFE using hybrid alternate clock scheme and baud-rate CDR in 65nm CMOS","authors":"S. Yuan, Liji Wu, Ziqiang Wang, Xuqiang Zheng, Peng Wang, Wen Jia, Chun Zhang, Zhihua Wang","doi":"10.1109/ESSCIRC.2015.7313849","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313849","url":null,"abstract":"A source-synchronous serial link receiver with an adaptive quarter-rate 2-tap DFE and a baud-rate CDR is demonstrated. The data-sampler-lane (DSL) of the DFE uses the combination of the soft-decision technique and a new dynamic structure to achieve a power efficiency of 0.24mW/Gb/s. The error-sampler-lane (ESL) based on the same dynamic structure is shared by the DFE adaption logic and baud-rate CDR logic to save power and area. A hybrid alternate clock scheme is implemented to satisfy the timing requirement and reduce power consumption further. This receiver fabricated in 65nm CMOS operates from 15 to 28Gb/s, and compensates for a Nyquist channel loss of 32dB with 0.42UI timing margin at 25Gb/s for BER=10-12. The active area is 0.18mm2 and the power consumption is 48mW at 25Gb/s from a 1.2V supply.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75238679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A ΣΔ based direct all-digital frequency synthesizer with 20 Mbps frequency modulation capability and 3μs startup latency 基于ΣΔ的直接全数字频率合成器，具有20 Mbps的调频能力和3μs的启动延迟
ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC) Pub Date : 2015-11-02 DOI: 10.1109/ESSCIRC.2015.7313909
R. Thirunarayanan, D. Ruffieux, N. Scolari, C. Enz
{"title":"A ΣΔ based direct all-digital frequency synthesizer with 20 Mbps frequency modulation capability and 3μs startup latency","authors":"R. Thirunarayanan, D. Ruffieux, N. Scolari, C. Enz","doi":"10.1109/ESSCIRC.2015.7313909","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313909","url":null,"abstract":"This paper presents an all-digital, direct frequency synthesizer that can support direct modulation data rates up to 20 Mbps for deployment in multi-hop, reconfigurable wireless mesh networks. In addition, this synthesizer can start up in only 3 us which reduces the energy overhead, thus making it attractive for duty cycling. By digitally manipulating time-shifted copies of a temperature-compensated FBAR oscillator signal based on the outputs from a Sigma-Delta modulator (SDM), the synthesizer is able to generate the desired frequency over a wide range. Integrated in a 65 nm CMOS technology, a prototype of this synthesizer generates frequencies from 2.34-2.47 GHz. Being completely digital, this synthesizer occupies a very small area of just 0.035 mm2. The synthesizer consumes 3.9 mA from a 1.1 V supply while achieving a frequency resolution of 180 Hz.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78854589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Low voltage error resilient SRAM using run-time error detection and correction 使用运行时错误检测和校正的低电压错误弹性SRAM
ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC) Pub Date : 2015-11-02 DOI: 10.1109/ESSCIRC.2015.7313895
Ashish Kumar, G. Visweswaran, K. Saha
{"title":"Low voltage error resilient SRAM using run-time error detection and correction","authors":"Ashish Kumar, G. Visweswaran, K. Saha","doi":"10.1109/ESSCIRC.2015.7313895","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313895","url":null,"abstract":"An adaptive SRAM architecture that can dynamically detect and correct read and write failures is discussed. The proposed method detects the failures, extends the failing cycles and subsequently corrects those. Data in the failing clock cycle are discarded and are made available in the subsequent cycle, if the failure is corrected. To detect write failures an adaptive write technique based on dummy write column is used. While for the read failures, the proposed read technique uses two non-identical sense amplifiers. We could achieve a Vmin lowering of 180mV for a 90nm ultra low power, high density 6T CMOS SRAM with less than 0.1 percent impact on throughput. This has been achieved without using assist-circuits or ECC. Area overhead is 3 percent for a 128Kb memory instance.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88677122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 124 to 132.5 GHz frequency quadrupler with 4.4 dBm output power in 0.13μm SiGe BiCMOS 一个124至132.5 GHz频率四倍器，输出功率4.4 dBm，采用0.13μm SiGe BiCMOS
ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC) Pub Date : 2015-11-02 DOI: 10.1109/ESSCIRC.2015.7313846
Yihu Li, W. Goh, Y. Xiong
{"title":"A 124 to 132.5 GHz frequency quadrupler with 4.4 dBm output power in 0.13μm SiGe BiCMOS","authors":"Yihu Li, W. Goh, Y. Xiong","doi":"10.1109/ESSCIRC.2015.7313846","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313846","url":null,"abstract":"In this paper, a 124-132.5 GHz frequency quadrupler using inter coupling superposition (ICS) technique is presented. A phase shifting buffer based on distributed structure is designed to switch on and off the quadrupler cells orthogonally; with the concept of inter cell coupling, each quadrupler cell generates \"W\" shape signal during `ON' state and behaves as negative impedance to provide extra signal power to the output port when it is in `OFF' state. The outputs of the four quadrupler cells are finally added to be in phase. Through the above output power enhancement techniques, a 4.4 dBm maximum output power at 130 GHz is achieved, with power efficiency of 10.6/2.4% (without/with buffers). The 0.13μm SiGe BiCMOS process is used to fabricate the design and the quadrupler core and the buffers consume 26mW and 89mW of DC power, respectively.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88408803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A low-noise programmable-gain amplifier for 25 Gb/s multi-mode fiber receivers in 28nm CMOS FDSOI 用于25gb /s多模光纤接收机的28nm CMOS FDSOI低噪声可编程增益放大器
ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC) Pub Date : 2015-11-02 DOI: 10.1109/ESSCIRC.2015.7313853
F. Radice, M. Bruccoleri, E. Mammei, M. Bassi, A. Mazzanti
{"title":"A low-noise programmable-gain amplifier for 25 Gb/s multi-mode fiber receivers in 28nm CMOS FDSOI","authors":"F. Radice, M. Bruccoleri, E. Mammei, M. Bassi, A. Mazzanti","doi":"10.1109/ESSCIRC.2015.7313853","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313853","url":null,"abstract":"Wide bandwidth, very low noise and high gain, finely adjustable, are key features in programmable-gain amplifiers (PGA) employed in multi-mode fiber (MMF) receivers. High frequency boost at Nyquist is also desirable to partially recover ISI and relax the requirements of electronic dispersion compensation. In this work, a PGA for 25Gb/s MMF receivers is proposed. Shunt and series inductors between cascaded stages are exploited to achieve programmable high-frequency boost independent from in-band gain and with a sharp out-of-band roll-off. Compared to typical RC-degenerated gain stages, the adopted solution enables very low noise operation. Realized in 28nm CMOS FDSOI technology the PGA has a programmable gain ranging from 15dB to 29dB with 0.15 dB fine steps and up to 14.2dB boost at Nyquist frequency. Power consumption is 32mW and equivalent input noise, at maximum high-frequency boost, is 300μVrms only.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89944208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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