{"title":"A 124 to 132.5 GHz frequency quadrupler with 4.4 dBm output power in 0.13μm SiGe BiCMOS","authors":"Yihu Li, W. Goh, Y. Xiong","doi":"10.1109/ESSCIRC.2015.7313846","DOIUrl":null,"url":null,"abstract":"In this paper, a 124-132.5 GHz frequency quadrupler using inter coupling superposition (ICS) technique is presented. A phase shifting buffer based on distributed structure is designed to switch on and off the quadrupler cells orthogonally; with the concept of inter cell coupling, each quadrupler cell generates \"W\" shape signal during `ON' state and behaves as negative impedance to provide extra signal power to the output port when it is in `OFF' state. The outputs of the four quadrupler cells are finally added to be in phase. Through the above output power enhancement techniques, a 4.4 dBm maximum output power at 130 GHz is achieved, with power efficiency of 10.6/2.4% (without/with buffers). The 0.13μm SiGe BiCMOS process is used to fabricate the design and the quadrupler core and the buffers consume 26mW and 89mW of DC power, respectively.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2015.7313846","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10
Abstract
In this paper, a 124-132.5 GHz frequency quadrupler using inter coupling superposition (ICS) technique is presented. A phase shifting buffer based on distributed structure is designed to switch on and off the quadrupler cells orthogonally; with the concept of inter cell coupling, each quadrupler cell generates "W" shape signal during `ON' state and behaves as negative impedance to provide extra signal power to the output port when it is in `OFF' state. The outputs of the four quadrupler cells are finally added to be in phase. Through the above output power enhancement techniques, a 4.4 dBm maximum output power at 130 GHz is achieved, with power efficiency of 10.6/2.4% (without/with buffers). The 0.13μm SiGe BiCMOS process is used to fabricate the design and the quadrupler core and the buffers consume 26mW and 89mW of DC power, respectively.