一种用于评价后处理CMOS芯片中MOSFET栅极介电界面态密度的BIST结构

ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC) Pub Date : 2015-11-02 DOI:10.1109/ESSCIRC.2015.7313915

N. Dodel, S. Keil, Andreas Wiemhofer, Malte Kortstock, P. Scholz, U. Kerst, R. Thewes

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摘要

提出了一种高精度的内置自检(BIST)结构，用于检测CMOS芯片MOS晶体管的栅极介电界面态密度。不需要特定的测量装置或设备。界面态密度直接进行A/D转换。该结构可以很容易地集成到任何具有标准数字接口的芯片中。

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A BIST structure for the evaluation of the MOSFET gate dielectric interface state density in post-processed CMOS chips

A highly accurate built-in-self-test (BIST) structure is presented which reveals the gate dielectric interface state density of the MOS transistors of CMOS chips. A specific measurement setup or equipment is not required. The interface state density is directly A/D converted. The structure can be easily integrated into any chip with a standard digital interface.

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ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)

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