A 48mW 15-to-28Gb/s source-synchronous receiver with adaptive DFE using hybrid alternate clock scheme and baud-rate CDR in 65nm CMOS

S. Yuan, Liji Wu, Ziqiang Wang, Xuqiang Zheng, Peng Wang, Wen Jia, Chun Zhang, Zhihua Wang
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引用次数: 2

Abstract

A source-synchronous serial link receiver with an adaptive quarter-rate 2-tap DFE and a baud-rate CDR is demonstrated. The data-sampler-lane (DSL) of the DFE uses the combination of the soft-decision technique and a new dynamic structure to achieve a power efficiency of 0.24mW/Gb/s. The error-sampler-lane (ESL) based on the same dynamic structure is shared by the DFE adaption logic and baud-rate CDR logic to save power and area. A hybrid alternate clock scheme is implemented to satisfy the timing requirement and reduce power consumption further. This receiver fabricated in 65nm CMOS operates from 15 to 28Gb/s, and compensates for a Nyquist channel loss of 32dB with 0.42UI timing margin at 25Gb/s for BER=10-12. The active area is 0.18mm2 and the power consumption is 48mW at 25Gb/s from a 1.2V supply.
采用混合备用时钟方案和65nm CMOS波特率CDR的48mW 15- 28gb /s源同步接收机
演示了一种具有自适应四分之一速率2分接DFE和波特率CDR的源同步串行链路接收器。DFE的数据采样通道(DSL)采用了软判决技术和一种新的动态结构相结合,功率效率达到0.24mW/Gb/s。基于相同动态结构的错误采样通道(ESL)由DFE自适应逻辑和波特率CDR逻辑共享,以节省功耗和面积。为了满足时序要求和进一步降低功耗,采用了一种混合备用时钟方案。该接收机采用65nm CMOS工艺,工作速率为15 ~ 28Gb/s,在BER=10-12的情况下,在25Gb/s下以0.42UI的时间余量补偿了32dB的奈奎斯特信道损耗。有效面积为0.18mm2,功耗为48mW,电源为1.2V,功率为25Gb/s。
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