R. Thirunarayanan, D. Ruffieux, N. Scolari, C. Enz
{"title":"A ΣΔ based direct all-digital frequency synthesizer with 20 Mbps frequency modulation capability and 3μs startup latency","authors":"R. Thirunarayanan, D. Ruffieux, N. Scolari, C. Enz","doi":"10.1109/ESSCIRC.2015.7313909","DOIUrl":null,"url":null,"abstract":"This paper presents an all-digital, direct frequency synthesizer that can support direct modulation data rates up to 20 Mbps for deployment in multi-hop, reconfigurable wireless mesh networks. In addition, this synthesizer can start up in only 3 us which reduces the energy overhead, thus making it attractive for duty cycling. By digitally manipulating time-shifted copies of a temperature-compensated FBAR oscillator signal based on the outputs from a Sigma-Delta modulator (SDM), the synthesizer is able to generate the desired frequency over a wide range. Integrated in a 65 nm CMOS technology, a prototype of this synthesizer generates frequencies from 2.34-2.47 GHz. Being completely digital, this synthesizer occupies a very small area of just 0.035 mm2. The synthesizer consumes 3.9 mA from a 1.1 V supply while achieving a frequency resolution of 180 Hz.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2015.7313909","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
This paper presents an all-digital, direct frequency synthesizer that can support direct modulation data rates up to 20 Mbps for deployment in multi-hop, reconfigurable wireless mesh networks. In addition, this synthesizer can start up in only 3 us which reduces the energy overhead, thus making it attractive for duty cycling. By digitally manipulating time-shifted copies of a temperature-compensated FBAR oscillator signal based on the outputs from a Sigma-Delta modulator (SDM), the synthesizer is able to generate the desired frequency over a wide range. Integrated in a 65 nm CMOS technology, a prototype of this synthesizer generates frequencies from 2.34-2.47 GHz. Being completely digital, this synthesizer occupies a very small area of just 0.035 mm2. The synthesizer consumes 3.9 mA from a 1.1 V supply while achieving a frequency resolution of 180 Hz.