一个124至132.5 GHz频率四倍器，输出功率4.4 dBm，采用0.13μm SiGe BiCMOS

ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC) Pub Date : 2015-11-02 DOI:10.1109/ESSCIRC.2015.7313846

Yihu Li, W. Goh, Y. Xiong

{"title":"一个124至132.5 GHz频率四倍器，输出功率4.4 dBm，采用0.13μm SiGe BiCMOS","authors":"Yihu Li, W. Goh, Y. Xiong","doi":"10.1109/ESSCIRC.2015.7313846","DOIUrl":null,"url":null,"abstract":"In this paper, a 124-132.5 GHz frequency quadrupler using inter coupling superposition (ICS) technique is presented. A phase shifting buffer based on distributed structure is designed to switch on and off the quadrupler cells orthogonally; with the concept of inter cell coupling, each quadrupler cell generates \"W\" shape signal during `ON' state and behaves as negative impedance to provide extra signal power to the output port when it is in `OFF' state. The outputs of the four quadrupler cells are finally added to be in phase. Through the above output power enhancement techniques, a 4.4 dBm maximum output power at 130 GHz is achieved, with power efficiency of 10.6/2.4% (without/with buffers). The 0.13μm SiGe BiCMOS process is used to fabricate the design and the quadrupler core and the buffers consume 26mW and 89mW of DC power, respectively.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"A 124 to 132.5 GHz frequency quadrupler with 4.4 dBm output power in 0.13μm SiGe BiCMOS\",\"authors\":\"Yihu Li, W. Goh, Y. Xiong\",\"doi\":\"10.1109/ESSCIRC.2015.7313846\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a 124-132.5 GHz frequency quadrupler using inter coupling superposition (ICS) technique is presented. A phase shifting buffer based on distributed structure is designed to switch on and off the quadrupler cells orthogonally; with the concept of inter cell coupling, each quadrupler cell generates \\\"W\\\" shape signal during `ON' state and behaves as negative impedance to provide extra signal power to the output port when it is in `OFF' state. The outputs of the four quadrupler cells are finally added to be in phase. Through the above output power enhancement techniques, a 4.4 dBm maximum output power at 130 GHz is achieved, with power efficiency of 10.6/2.4% (without/with buffers). The 0.13μm SiGe BiCMOS process is used to fabricate the design and the quadrupler core and the buffers consume 26mW and 89mW of DC power, respectively.\",\"PeriodicalId\":11845,\"journal\":{\"name\":\"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-11-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.2015.7313846\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2015.7313846","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 10

摘要

本文提出了一种采用内耦合叠加(ICS)技术的124-132.5 GHz频率四倍器。设计了一种基于分布式结构的相移缓冲器，用于正交地接通和关闭四倍器单元;利用单元间耦合的概念，每个四倍器单元在“开”状态下产生“W”形信号，并在“关”状态下作为负阻抗向输出端口提供额外的信号功率。最后将四个四倍器单元的输出加到同相中。通过上述输出功率增强技术，可实现130 GHz时4.4 dBm的最大输出功率，功率效率为10.6/2.4%(无/带缓冲器)。该设计采用0.13μm SiGe BiCMOS工艺，四倍器核心和缓冲器分别消耗26mW和89mW的直流功率。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A 124 to 132.5 GHz frequency quadrupler with 4.4 dBm output power in 0.13μm SiGe BiCMOS

In this paper, a 124-132.5 GHz frequency quadrupler using inter coupling superposition (ICS) technique is presented. A phase shifting buffer based on distributed structure is designed to switch on and off the quadrupler cells orthogonally; with the concept of inter cell coupling, each quadrupler cell generates "W" shape signal during `ON' state and behaves as negative impedance to provide extra signal power to the output port when it is in `OFF' state. The outputs of the four quadrupler cells are finally added to be in phase. Through the above output power enhancement techniques, a 4.4 dBm maximum output power at 130 GHz is achieved, with power efficiency of 10.6/2.4% (without/with buffers). The 0.13μm SiGe BiCMOS process is used to fabricate the design and the quadrupler core and the buffers consume 26mW and 89mW of DC power, respectively.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)

自引率

0.00%

发文量