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2016 16th International Workshop on Junction Technology (IWJT)最新文献

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P+-Ge1−xSnx / p−-Ge1−x−ySixSny / n-Ge1−x−ySixSny NTFET analysis and the realization of n-Ge1−x−ySixSny ohmic contact P+-Ge1−xSnx / P−-Ge1−x−ySixSny / n-Ge1−x−ySixSny NTFET分析及n-Ge1−x−ySixSny欧姆接触的实现
2016 16th International Workshop on Junction Technology (IWJT) Pub Date : 2016-05-09 DOI: 10.1109/IWJT.2016.7486667
Suyuan Wang, Jun Zheng, C. Xue, Chuanbo Li, Y. Zuo, B. Cheng, Qiming Wang
{"title":"P+-Ge1−xSnx / p−-Ge1−x−ySixSny / n-Ge1−x−ySixSny NTFET analysis and the realization of n-Ge1−x−ySixSny ohmic contact","authors":"Suyuan Wang, Jun Zheng, C. Xue, Chuanbo Li, Y. Zuo, B. Cheng, Qiming Wang","doi":"10.1109/IWJT.2016.7486667","DOIUrl":"https://doi.org/10.1109/IWJT.2016.7486667","url":null,"abstract":"In this paper, n-Ge1-x-ySixSny ternary alloy was successfully grown by using the Sb in situ doping technique through sputter epitaxy method. Ohmic contacts to n-Ge1-x-ySixSny are realized by shallow P implant. Group IV heterostructure p<sup>+</sup>-Ge<sub>1-x</sub>Sn<sub>x</sub> / p<sup>-</sup>-Ge<sub>1-x-y</sub>Si<sub>x</sub>Sn<sub>y</sub> / n-Ge<sub>1-x-y</sub>Si<sub>x</sub>Sn<sub>y</sub> N-channel tunneling field-effect transistor (NTFET) is proposed and simulated. The narrow bandgap of Ge<sub>1-x</sub>Sn<sub>x</sub> increases the band-to-band-tunneling (BTBT) tunneling probability at Γ valley, which leads to a higher on-state current. The n-Ge<sub>1-x-y</sub>Si<sub>x</sub>Sn<sub>y</sub> is used as drain since it exhibits a large indirect bandgap, which reduces the ambipolar behavior in NTFET.","PeriodicalId":117665,"journal":{"name":"2016 16th International Workshop on Junction Technology (IWJT)","volume":"04 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127258331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Anisotropic strain evaluation induced in group IV materials using liquid-immersion Raman spectroscopy 用液浸拉曼光谱对IV类材料进行各向异性应变评价
2016 16th International Workshop on Junction Technology (IWJT) Pub Date : 2016-05-09 DOI: 10.1109/IWJT.2016.7486679
A. Ogura, K. Takeuchi
{"title":"Anisotropic strain evaluation induced in group IV materials using liquid-immersion Raman spectroscopy","authors":"A. Ogura, K. Takeuchi","doi":"10.1109/IWJT.2016.7486679","DOIUrl":"https://doi.org/10.1109/IWJT.2016.7486679","url":null,"abstract":"We evaluated anisotropic biaxial strain induced in silicon channel region of metal-oxide-semiconductor field effect transistor (MOSFET) as well as novel channel or source/drain materials such as silicon germanium (SiGe) and germanium tin (GeSn) using liquid-immersion Raman spectroscopy. Uniaxial stress in Si channel region predicted by the simulation was well reproduced by Raman measurement. For the evaluation of SiGe and GeSn, the phonon deformation potentials (PDPs) were derived for the first time, because they are indispensable to obtain the biaxial strain. The PDPs of SiGe indicate clear Ge concentration dependence, which is decreasing with Ge concentration, while the PDPs of GeSn with less than 3.2% Sn concentration exhibit almost constant. Using the derived PDPs, we obtained the anisotropic biaxial strains introduced in the finite patterned SiGe precisely.","PeriodicalId":117665,"journal":{"name":"2016 16th International Workshop on Junction Technology (IWJT)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114388561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Challenges of 2-D (3-D) device doping process and doping profiling metrology 2-D (3-D)器件掺杂工艺和掺杂分析计量的挑战
2016 16th International Workshop on Junction Technology (IWJT) Pub Date : 2016-05-09 DOI: 10.1109/IWJT.2016.7486680
S. Qin
{"title":"Challenges of 2-D (3-D) device doping process and doping profiling metrology","authors":"S. Qin","doi":"10.1109/IWJT.2016.7486680","DOIUrl":"https://doi.org/10.1109/IWJT.2016.7486680","url":null,"abstract":"The appearance of 3-D devices and structures has changed the doping technologies and doping profiling metrology. This change also implies that novel concepts for 3-D dopant and carrier profiling measurements are necessary. 1.5-D SIMS can be used to study dopant incorporation in 3-D structures. SSRM and electron holography methods have been developed and well-established on 2-D cross-sectional doping profiling measurements. Although SSRM and electron holography approaches are inherently 2-D, extensions towards 3-D structures are capable either by the dedicated design of test structures or by the approaches of mechanical slicing and polishing. Thanks to the new 2-D (3-D) doping profiling measurements, PLAD process has been demonstrated beneficial on 3-D device manufacturing.","PeriodicalId":117665,"journal":{"name":"2016 16th International Workshop on Junction Technology (IWJT)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114860186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
10 nm-deep n+/p and p+/n Ge junctions with high activation formed by ion implantation and Flash Lamp Annealing (FLA) 离子注入和闪光灯退火(FLA)形成的10 nm深n+/p和p+/n Ge高活化结
2016 16th International Workshop on Junction Technology (IWJT) Pub Date : 2016-05-09 DOI: 10.1109/IWJT.2016.7486678
H. Tanimura, H. Kawarazaki, K. Fuse, M. Abe, T. Yamada, Y. Ono, M. Furukawa, A. Ueda, Y. Ito, T. Aoyama, S. Kato, I. Kobayashi, H. Onoda, Y. Nakashima, T. Nagayama, N. Hamamoto, S. Sakai
{"title":"10 nm-deep n+/p and p+/n Ge junctions with high activation formed by ion implantation and Flash Lamp Annealing (FLA)","authors":"H. Tanimura, H. Kawarazaki, K. Fuse, M. Abe, T. Yamada, Y. Ono, M. Furukawa, A. Ueda, Y. Ito, T. Aoyama, S. Kato, I. Kobayashi, H. Onoda, Y. Nakashima, T. Nagayama, N. Hamamoto, S. Sakai","doi":"10.1109/IWJT.2016.7486678","DOIUrl":"https://doi.org/10.1109/IWJT.2016.7486678","url":null,"abstract":"In this paper, we report on the formation of shallow junctions with high activation in both n+/p and p+/n Ge junctions using ion implantation and Flash Lamp Annealing (FLA). The shallowest junction depths formed for the n+/p and p+/n junctions were 9.5 nm and 10.7 nm with sheet resistances of 620 ohms/sq. and 414 ohms/sq., respectively. Additionally, by reducing knocked-on oxygen during ion implantation, the sheet resistance was decreased by 5 to 15%. The lowest sheet resistance was 235 ohms/sq. with a junction depth of 21.5 nm in the n+/p Ge. These results indicate that the potential for forming ultra-shallow n+/p and p+/n junctions in the nanometer range in Ge devices using FLA is very high, leading to realistic monolithically-integrated Ge CMOS devices.","PeriodicalId":117665,"journal":{"name":"2016 16th International Workshop on Junction Technology (IWJT)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122901902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
MIS or MS? Source/drain contact scheme evaluation for 7nm Si CMOS technology and beyond MIS还是MS?7nm Si CMOS及以上技术的源/漏极接触方案评估
2016 16th International Workshop on Junction Technology (IWJT) Pub Date : 2016-05-09 DOI: 10.1109/IWJT.2016.7486665
Hao Yu, M. Schaekers, S. Demuynck, K. Barla, A. Mocuta, N. Horiguchi, N. Collaert, A. Thean, K. De Meyer
{"title":"MIS or MS? Source/drain contact scheme evaluation for 7nm Si CMOS technology and beyond","authors":"Hao Yu, M. Schaekers, S. Demuynck, K. Barla, A. Mocuta, N. Horiguchi, N. Collaert, A. Thean, K. De Meyer","doi":"10.1109/IWJT.2016.7486665","DOIUrl":"https://doi.org/10.1109/IWJT.2016.7486665","url":null,"abstract":"Contact resistance at the transistor source/drain becomes a bottleneck for modern Si CMOS technology. To seek for contact solutions, this paper compares metal-insulator-semiconductor (MIS) contacts and metal-semiconductor (MS) direct contacts in terms of contact resistivity and CMOS compatibility. On p-type substrates, due to the favorable surface Fermi level pinning, MS contact has absolute advantage over MIS. On n-type substrates, on the one hand, we find MIS contacts have relatively high contact resistivity despite the low Schottky barrier height; the low thermal stability of MIS is also worrying. On the other hand, with MS contacts, we use a pre-amorphization based Ti silicidation technique and achieve contact resistivity of 1.5×10-9 Ω·cm2. Therefore, for both NMOS and PMOS, we confirm that MS contacts are still the prevailing contact scheme. Advanced MS interface engineering is able to help reach the target contact resistivity required by advanced CMOS technology.","PeriodicalId":117665,"journal":{"name":"2016 16th International Workshop on Junction Technology (IWJT)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121149037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Activation of impurity atoms in 4H-SiC wafer by atmospheric pressure thermal plasma jet irradiation 常压热等离子体射流辐照4H-SiC晶圆中杂质原子的活化
2016 16th International Workshop on Junction Technology (IWJT) Pub Date : 2016-05-09 DOI: 10.1109/IWJT.2016.7486676
S. Higashi, K. Maruyama, H. Hanafusa
{"title":"Activation of impurity atoms in 4H-SiC wafer by atmospheric pressure thermal plasma jet irradiation","authors":"S. Higashi, K. Maruyama, H. Hanafusa","doi":"10.1109/IWJT.2016.7486676","DOIUrl":"https://doi.org/10.1109/IWJT.2016.7486676","url":null,"abstract":"High temperature annealing of 4H-silicon carbide (SiC) wafers was performed by atmospheric-pressure thermal-plasma-jet (TPJ) irradiation. A maximum surface temperature of 1835°C within 2.4 second without sample breakage was achieved, and aluminum (Al), phosphorus (P), and arsenic (As) activations in 4H-SiC wafers were demonstrated. We have investigated the effects of heating rate (R<sub>h</sub>) and cooling rate (R<sub>c</sub>) during rapid annealing of P-implanted 4H-SiC on the activation efficiency. No dependence of resistivity on R<sub>h</sub> was observed, while increasing Rc significantly decreased resistivity. The minimum resistivity of 0.0025 Ω·cm, the maximum electron concentration of 2.9 × 10<sup>20</sup> cm<sup>-3</sup>, respectively, were obtained under R<sub>c</sub> = 568 °C /s.","PeriodicalId":117665,"journal":{"name":"2016 16th International Workshop on Junction Technology (IWJT)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127253794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Device performance improvement with implantation balancing energy contamination and productivity 通过植入平衡能量污染和生产效率来改善设备性能
2016 16th International Workshop on Junction Technology (IWJT) Pub Date : 2016-05-09 DOI: 10.1109/IWJT.2016.7486672
Yonggen He, G. Cai, Zuyuan Zhou, Youfeng He, Jingang Wu, David-Wei Zhang, Ting Cai, Junfeng Lu, Ganming Zhao, B. Guo
{"title":"Device performance improvement with implantation balancing energy contamination and productivity","authors":"Yonggen He, G. Cai, Zuyuan Zhou, Youfeng He, Jingang Wu, David-Wei Zhang, Ting Cai, Junfeng Lu, Ganming Zhao, B. Guo","doi":"10.1109/IWJT.2016.7486672","DOIUrl":"https://doi.org/10.1109/IWJT.2016.7486672","url":null,"abstract":"Ion implantation technology is widely used in semiconductor manufacturing process. Most of install base for high current implanters use deceleration technology to overcome space charge effect especially important for low energy implants. It is necessary to consider the Energy contamination (EC) effects on devices with thinner gate height. This paper use SRIM simulation and dopant profiles, offline sheet resistance to illustrate the selection of deceleration by considering EC tails beyond the gate height. The device effects using p-type Poly (PPoly) and Source Drain (PSD) implant steps are evaluated in state of art 28nm device flow. The device performance can gain 6% with optimized implant conditions. It demonstrated the necessary of balance device requirement and productivity using implanters with deceleration technologies. The newer generation implanters with EC filter technology, providing maximum productivity while meeting device requirement, was discussed briefly also.","PeriodicalId":117665,"journal":{"name":"2016 16th International Workshop on Junction Technology (IWJT)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122344854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A novel high-voltage LDMOS with Folded Drift Region 一种具有折叠漂移区的新型高压LDMOS
2016 16th International Workshop on Junction Technology (IWJT) Pub Date : 2016-05-09 DOI: 10.1109/IWJT.2016.7486668
Ling Du, Yufeng Guo, Jiafei Yao, Jun Zhang, Kemeng Yang, Man Li
{"title":"A novel high-voltage LDMOS with Folded Drift Region","authors":"Ling Du, Yufeng Guo, Jiafei Yao, Jun Zhang, Kemeng Yang, Man Li","doi":"10.1109/IWJT.2016.7486668","DOIUrl":"https://doi.org/10.1109/IWJT.2016.7486668","url":null,"abstract":"This paper proposes a novel high-voltage LDMOS with Folded Drift Region (FDR) structure. The structure extends the effective length of the current path in the limited drift region length, and uniformthe electric field profile in order to have a high breakdown voltage. The structure parameters are optimized and the characteristics are investigated by a 2D device simulator MEDICI. The simulation results show that the electric field, breakdown voltage, and specific on-resistance are effectively improved when compared with those of the conventional device. A breakdown voltage over 600V is obtained on the proposed LDMOS with 10μm thick silicon layer, 3μm buried oxide and 28μm drift region length.","PeriodicalId":117665,"journal":{"name":"2016 16th International Workshop on Junction Technology (IWJT)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126660331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Ohmic contacts for AlGaN/GaN HEMTs with artificially introduced uneven structures at metal/AlGaN interfaces 在金属/AlGaN界面人工引入不均匀结构的AlGaN/GaN hemt的欧姆接触
2016 16th International Workshop on Junction Technology (IWJT) Pub Date : 2016-05-09 DOI: 10.1109/IWJT.2016.7486663
K. Tsutsui
{"title":"Ohmic contacts for AlGaN/GaN HEMTs with artificially introduced uneven structures at metal/AlGaN interfaces","authors":"K. Tsutsui","doi":"10.1109/IWJT.2016.7486663","DOIUrl":"https://doi.org/10.1109/IWJT.2016.7486663","url":null,"abstract":"A new approach to reduce contact resistance on AlGaN/GaN HEMTs, in which an inherent tradeoff involving the AlGaN layer thickness exists, is discussed. This method introduced uneven AlGaN layer structures under the ohmic contact metal layers. The fringing effect where the AlGaN layer thickness fluctuates plays an important role. Effects of horizontal pattern features and their size, in other words, pattern density were investigated.","PeriodicalId":117665,"journal":{"name":"2016 16th International Workshop on Junction Technology (IWJT)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130056230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Ion implant technology for state-of-the-art high efficiency solar cell applications 离子植入技术用于最先进的高效太阳能电池应用
2016 16th International Workshop on Junction Technology (IWJT) Pub Date : 2016-05-09 DOI: 10.1109/IWJT.2016.7486674
Guangyao Jin, Yaojie Sun, Yizhe Wang, David-Wei Zhang, Lin Chen, Chuan He, J. Boeker, J. Hong, Shoujun Chen, Renjie Liu, Yimin Lv, J. Chen
{"title":"Ion implant technology for state-of-the-art high efficiency solar cell applications","authors":"Guangyao Jin, Yaojie Sun, Yizhe Wang, David-Wei Zhang, Lin Chen, Chuan He, J. Boeker, J. Hong, Shoujun Chen, Renjie Liu, Yimin Lv, J. Chen","doi":"10.1109/IWJT.2016.7486674","DOIUrl":"https://doi.org/10.1109/IWJT.2016.7486674","url":null,"abstract":"For many years, Photovoltaic (PV) solar technology was believed not possible to be cost effective and not even close to the cost for electricity production compared to fossil fuels. Surprisingly, the fact is that low cost but powerful and long-lasting solar modules can now be mass produced at the scale of over 60GW per year which makes the LCOE (levelizedcost of electricity) of latest PV systemcost competitive with any other technologies. Similarly, for ion implant technology in solar applications, which were thought to be too slow and expensive, have been successfully been utilized in current solar cell mass production as well as producing of state-of-the-art high efficiency solar cells. The development of ion implant processes for solar cells and the latest high efficiency solar cell results will be presented in this paper.","PeriodicalId":117665,"journal":{"name":"2016 16th International Workshop on Junction Technology (IWJT)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133048328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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