H. Tanimura, H. Kawarazaki, K. Fuse, M. Abe, T. Yamada, Y. Ono, M. Furukawa, A. Ueda, Y. Ito, T. Aoyama, S. Kato, I. Kobayashi, H. Onoda, Y. Nakashima, T. Nagayama, N. Hamamoto, S. Sakai
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引用次数: 5
Abstract
In this paper, we report on the formation of shallow junctions with high activation in both n+/p and p+/n Ge junctions using ion implantation and Flash Lamp Annealing (FLA). The shallowest junction depths formed for the n+/p and p+/n junctions were 9.5 nm and 10.7 nm with sheet resistances of 620 ohms/sq. and 414 ohms/sq., respectively. Additionally, by reducing knocked-on oxygen during ion implantation, the sheet resistance was decreased by 5 to 15%. The lowest sheet resistance was 235 ohms/sq. with a junction depth of 21.5 nm in the n+/p Ge. These results indicate that the potential for forming ultra-shallow n+/p and p+/n junctions in the nanometer range in Ge devices using FLA is very high, leading to realistic monolithically-integrated Ge CMOS devices.
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