A novel high-voltage LDMOS with Folded Drift Region

Abstract

This paper proposes a novel high-voltage LDMOS with Folded Drift Region (FDR) structure. The structure extends the effective length of the current path in the limited drift region length, and uniformthe electric field profile in order to have a high breakdown voltage. The structure parameters are optimized and the characteristics are investigated by a 2D device simulator MEDICI. The simulation results show that the electric field, breakdown voltage, and specific on-resistance are effectively improved when compared with those of the conventional device. A breakdown voltage over 600V is obtained on the proposed LDMOS with 10μm thick silicon layer, 3μm buried oxide and 28μm drift region length.