Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)最新文献_第2页

Quality of electronic design: from architectural level to test coverage 电子设计的质量:从架构层面到测试覆盖

Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525) Pub Date : 2000-03-20 DOI: 10.1109/ISQED.2000.838874

O. P. Dias, J. Semião, Marcelino B. Santos, I. Teixeira, João Paulo Teixeira

引用次数: 2

DVDT: design for voltage drop test using on-chip voltage scan path DVDT:使用片上电压扫描路径设计电压降测试

Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525) Pub Date : 2000-03-20 DOI: 10.1109/ISQED.2000.838887

M. Ikeda, H. Aoki, K. Asada

引用次数: 0

Peak power reduction in low power BIST 低功率BIST的峰值功率降低

Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525) Pub Date : 2000-03-20 DOI: 10.1109/ISQED.2000.838911

Xiaodong Zhang, K. Roy

引用次数: 21

An efficient rule-based OPC approach using a DRC tool for 0.18 /spl mu/m ASIC 一种高效的基于规则的OPC方法，使用DRC工具用于0.18 /spl mu/m ASIC

Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525) Pub Date : 2000-03-20 DOI: 10.1109/ISQED.2000.838858

Ji-Soong Park, Chul-Hong Park, Sang-Uhk Rhie, Yoo-Hyon Kim, Moon-Hyun Yoo, J. Kong, Hyung-Woo Kim, Sunjoo Yoo

引用次数: 23

EMI common-mode current dependence on delay skew imbalance in high speed differential transmission lines operating at 1 gigabit/second data rates 在1千兆位/秒数据速率的高速差分传输线中，EMI共模电流依赖于延迟倾斜不平衡

Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525) Pub Date : 2000-03-20 DOI: 10.1109/ISQED.2000.838888

J. Knighten, N. Smith, L. Hoeft, J. T. DiBene

引用次数: 12

Design for testability in nanometer technologies; searching for quality 纳米技术可测试性设计;寻找质量

Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525) Pub Date : 2000-03-20 DOI: 10.1109/ISQED.2000.838870

T. Williams, R. Kapur

引用次数: 1

Full chip thermal simulation 全芯片热模拟

Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525) Pub Date : 2000-03-20 DOI: 10.1109/ISQED.2000.838867

Zhiping Yu, D. Yergeau, R. Dutton, O. S. Nakagawa, N. Chang, Shen Lin, Weize Xie

{"title":"Full chip thermal simulation","authors":"Zhiping Yu, D. Yergeau, R. Dutton, O. S. Nakagawa, N. Chang, Shen Lin, Weize Xie","doi":"10.1109/ISQED.2000.838867","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838867","url":null,"abstract":"A multilayer, full chip thermal analysis is presented. The design of the chip at functional-block level is directly captured by the simulator, allowing the assessment of the chip layout impact on the system performance due to the elevated operational temperature. The heat generation for each block is obtained by running the circuit-level electrical simulation separately on individual functional units. The thermal diffusion equation is then solved based on the actual structure of the chip including substrate and interconnect/insulating layers. Different thermal conductivity can be specified for each material layer. The effect of package on chip temperature distribution is modeled using thermally resistive layers as the boundary between the simulated structure and surrounding environment. Proper adjustment of the boundary thermal resistance results in the correct range of simulated temperature distribution as compared to the measured data. Both physics and implementation for the thermal simulation are described. The code is applied to the analysis of a realistic design of a CPU chip made of SOI technology with up to six metal interconnect layers. A comprehensive review of the simulation results is presented.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130046092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 29

Applying the OpenMORE assessment program for IP cores 应用OpenMORE IP核评估程序

Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525) Pub Date : 2000-03-20 DOI: 10.1109/ISQED.2000.838900

Jean-Pierre Gukguen, P. Bricaud

引用次数: 4

Aliasing-free space and time compactions with limited overhead 无混叠的空间和时间压缩，开销有限

Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525) Pub Date : 2000-03-20 DOI: 10.1109/ISQED.2000.838896

Jin Ding, D. Moloney, Xiaojun Wang

{"title":"Aliasing-free space and time compactions with limited overhead","authors":"Jin Ding, D. Moloney, Xiaojun Wang","doi":"10.1109/ISQED.2000.838896","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838896","url":null,"abstract":"Space- and time-oriented compactions are to reduce the output response data width and length of circuits under test for built-in self-test technique. In this paper, the space- and time-oriented compaction techniques are considered together. First, the space-oriented data compaction technique is analyzed. We present a scheme, which can compress the data of k-output circuit into 1-bit signature stream with zero-aliasing and zero-performance-degradation for single stuck-line faults. Based on the investigation of the space's odd-sensitized and space's even-sensitized faults of the circuits under test, we discuss the compact methods of space's odd sensitization and space's even sensitization test responses, respectively. The graph coloring is adopted to decrease space compactor overhead. The coloring complexity is greatly decreased owing to only painting the output notes with respect to the space's even-sensitized faults. Next, we take into account the time-oriented data compaction scheme. We use the property that a test vector detects multiple faults in the time's even sensitization response compaction. In the time-oriented compaction approach developed in this paper, an s-bit long data stream can be compressed to an r-bit signature with zero-aliasing, where s/spl Gt/r. Experimental results are presented to demonstrate the effectiveness of the proposed space- and time-oriented compaction techniques.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132641518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Probabilistic bottom-up RTL power estimation 概率自底向上RTL功率估计

Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525) Pub Date : 2000-03-20 DOI: 10.1109/ISQED.2000.838916

R. Ferreira, Anne-Marie Trullemans-Anckaert, José C. Costa, J. Monteiro

引用次数: 6