Design for testability in nanometer technologies; searching for quality

Abstract

Today's technology allows for the creation of designs that are stressing methodologies from a time to market point of view. The industry is in a transition period where the methodologies and tools are changing to allow for reusing designs as cores. With a promise of large capacity, the miniaturization of the devices brings along new problems and changes the focus of Design for Testability (DFT) and for all the tools used in the successful manufacturing of the design. In this paper, the impact of nanometer technology on the issues associated with testing of system-on-chip (SOC) designs is discussed.