Probabilistic bottom-up RTL power estimation

Abstract

We address the problem of power estimation at the register-transfer level (RTL). At this level, the circuit is described in terms of a set of interconnected memory elements and combinational modules of different degrees of complexity. We propose a bottom-up approach to create a simplified high-level model of the block behavior for power estimation, which is described by a symbolic local polynomial. We use an efficient gate-level modeling based on the polynomial simulation method and ZBDDs. We present a set of experimental results that show a large improvement in performance and robustness when compared to previous approaches.