DVDT: design for voltage drop test using on-chip voltage scan path

Abstract

This paper proposes a new design method for voltage drop testing using on-chip voltage scan path. Using on-chip voltage monitors with a scan path data transfer architecture, this on-chip voltage scan path can measure voltage-drop on a real chip in real time with a limited number of I/O pins. Preliminary results are presented based on measurement results using a test chip, which demonstrates that this technique can effectively monitor voltage bounce in power supply lines. Quality of power supply lines can be effectively enhanced when this technique is applied to a real chip.