Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)最新文献_第7页

Overview of SiGe technology modeling and application SiGe技术建模与应用概述

Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525) Pub Date : 2000-03-20 DOI: 10.1109/ISQED.2000.838856

J. Yuan

引用次数: 1

Early addressing IC and package relationship allows an overall better quality of complex SOC 早期的寻址IC和封装关系允许复杂SOC的整体质量更好

Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525) Pub Date : 2000-03-20 DOI: 10.1109/ISQED.2000.838864

A. Fontanelli, L. Arnone, R. Branca, Giorgio Mastrorocco

引用次数: 7

LEMINGS: LSI's EMI-noise analysis with gate level simulator 利用栅极电平模拟器分析LSI的emi噪声

Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525) Pub Date : 2000-03-20 DOI: 10.1109/ISQED.2000.838865

K. Shimazaki, H. Tsujikawa, Seijiro Kojima, Shouzou Hirano

{"title":"LEMINGS: LSI's EMI-noise analysis with gate level simulator","authors":"K. Shimazaki, H. Tsujikawa, Seijiro Kojima, Shouzou Hirano","doi":"10.1109/ISQED.2000.838865","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838865","url":null,"abstract":"EMI (electromagnetic interference) noise has become a more significant problem in high-speed electronic systems. To analyze EMI problems, LSIs should be analysed carefully as the source of EMI noise. However, as the circuit size of the LSIs becomes larger, it becomes more difficult to analyze the noise of these circuits by using a transistor-level simulator. Thus designers need a simulator that covers full-chip size for noise analysis. In this paper, we propose a new EMI noise simulation methodology that uses a gate-level representation for the first time. The noise from the logic gates is simply modeled by a FFT process based on the superimposed triangular current waveform. Because of the compactness of the model, we can reduce the computation dramatically and accomplish a large simulation. Furthermore, we developed a prototype simulator 'LEMINGS' to demonstrate the proposed method for conventional ASIC design flows. The experimental results show that our new EMI analysis method has achieved an outstanding performance, a high capacity to simulate the whole design and a high accuracy that is equivalent to the transistor-level simulator. Information obtained from LEMINGS can also help designers to improve the LSI and electronic systems' design quality.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129238408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18

A reliable clock tree design methodology for ASIC designs 一种用于ASIC设计的可靠时钟树设计方法

Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525) Pub Date : 2000-03-20 DOI: 10.1109/ISQED.2000.838882

Mely Chen Chi, Shih-Hsu Huang

{"title":"A reliable clock tree design methodology for ASIC designs","authors":"Mely Chen Chi, Shih-Hsu Huang","doi":"10.1109/ISQED.2000.838882","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838882","url":null,"abstract":"In the deep submicron era, an ASIC chip may contain millions of gates and have the requirements of low power and high performance. The ability to construct multiple clock trees effectively is very important. A clock tree design methodology is presented. Firstly, we conducted many clock tree synthesis experiments, which explored various configurations of clock tree structure and layouts. A guide for clock tree synthesis is then generated. By applying this guidance, the clock tree design procedure in ASIC design is simplified and the design time is shortened. The clock skews are within the expected range. This methodology has been used to implement clock trees on the chips designed in the Computer and Communications Research Laboratories. Our experience shows that for single clock trees the intra-clock skew is confined within 0.1 ns in one design pass for 0.35 /spl mu/m CMOS technology chips. For multiple clock trees, which are originated from the same clock source, the inter-clock skew may also be controlled easily. This design methodology is proven to be a reliable method to implement clock trees on ASIC chips.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116788383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Power bus maximum voltage drop in digital VLSI circuits 数字VLSI电路中的电源总线最大电压降

Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525) Pub Date : 1900-01-01 DOI: 10.1109/ISQED.2000.838881

G. Bai, S. Bobba, I. Hajj

引用次数: 6