A reliable clock tree design methodology for ASIC designs

Abstract

In the deep submicron era, an ASIC chip may contain millions of gates and have the requirements of low power and high performance. The ability to construct multiple clock trees effectively is very important. A clock tree design methodology is presented. Firstly, we conducted many clock tree synthesis experiments, which explored various configurations of clock tree structure and layouts. A guide for clock tree synthesis is then generated. By applying this guidance, the clock tree design procedure in ASIC design is simplified and the design time is shortened. The clock skews are within the expected range. This methodology has been used to implement clock trees on the chips designed in the Computer and Communications Research Laboratories. Our experience shows that for single clock trees the intra-clock skew is confined within 0.1 ns in one design pass for 0.35 /spl mu/m CMOS technology chips. For multiple clock trees, which are originated from the same clock source, the inter-clock skew may also be controlled easily. This design methodology is proven to be a reliable method to implement clock trees on ASIC chips.