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Proceedings of CICC 97 - Custom Integrated Circuits Conference最新文献

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Techniques for aggressive supply voltage scaling and efficient regulation [CMOS digital circuits] 积极的电源电压缩放和有效调节技术[CMOS数字电路]
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606693
A. Dancy, Anantha Chandrakasan
{"title":"Techniques for aggressive supply voltage scaling and efficient regulation [CMOS digital circuits]","authors":"A. Dancy, Anantha Chandrakasan","doi":"10.1109/CICC.1997.606693","DOIUrl":"https://doi.org/10.1109/CICC.1997.606693","url":null,"abstract":"Aggressive voltage scaling to 1 V and below through technology, circuit, and architecture optimization is the key to low-power design. Threshold voltage scaling enables aggressive supply scaling but increases leakage power. Technology and circuit trends to control idle leakage power are presented including MTCMOS, variable V/sub T/ bulk-CMOS, and variable V/sub T/ SOI. Power can also be reduced by adaptively varying the supply voltage in applications where the computational workload varies with time. Aggressive voltage and power level scaling requires efficient DC-DC conversion circuitry and in some cases, it is necessary to embed this function in the processor.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129054253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
A fully differential 1.5 V low-power CMOS operational amplifier with a rail-to-rail current-regulated constant-g/sub m/ input stage 一种全差分1.5 V低功耗CMOS运算放大器，具有轨对轨电流调节常数g/sub /输入级
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606588
E. Peeters, M. Steyaert, W. Sansen
{"title":"A fully differential 1.5 V low-power CMOS operational amplifier with a rail-to-rail current-regulated constant-g/sub m/ input stage","authors":"E. Peeters, M. Steyaert, W. Sansen","doi":"10.1109/CICC.1997.606588","DOIUrl":"https://doi.org/10.1109/CICC.1997.606588","url":null,"abstract":"This paper presents a compact fully differential amplifier with a rail-to-rail input stage and a class AB output stage. A new biasing scheme for a complementary rail-to-rail input stage with constant g/sub m/ is introduced. The proposed biasing scheme uses a current regulating loop to keep the sum of the biasing currents of the complementary input pairs constant. This results in a g/sub m/-variation below 4% for input pairs operating in weak inversion. In a standard 0.7 /spl mu/m CMOS technology the circuit can handle power supply voltages ranging from 1.5 V up to 3.3 V. For a power consumption of 300 /spl mu/W and a load capacitance of 15 pF a gainbandwidth (GBW) of 4.3 MHz is achieved. This results in a GBWCL-to-supply-power ratio of 210 MHz/spl middot/pF/mW. The total die area of the amplifier is 0.25 mm/sup 2/.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129063600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
A high-linearity low-voltage all-MOSFET delta-sigma modulator 一种高线性低电压全mosfet δ - σ调制器
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606632
Y. Huang, G. Temes, H. Yoshizawa
{"title":"A high-linearity low-voltage all-MOSFET delta-sigma modulator","authors":"Y. Huang, G. Temes, H. Yoshizawa","doi":"10.1109/CICC.1997.606632","DOIUrl":"https://doi.org/10.1109/CICC.1997.606632","url":null,"abstract":"The implementation of a second-order switched-capacitor delta-sigma modulator is described. The modulator uses MOSFETs in their accumulation region as capacitors, with the input branches linearized using series compensation. It utilizes only basic digital CMOS technology and was fabricated in a 1.2 /spl mu/m process. The chip area of the modulator is about 1 mm/sup 2/. Measured results show that the modulator has a 94 dB peak S/THD, a 96 dB peak S/N and an 86 dB peak S/THD+N for a 6 kHz bandwidth with 5.4 mW power dissipation using a 3 V power supply and a 3.6 V capacitor bias voltage.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"728 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116983793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
IO buffer for high performance, low-power application 用于高性能、低功耗应用的IO缓冲器
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606696
J. Shor, Y. Afek, E. Engel
{"title":"IO buffer for high performance, low-power application","authors":"J. Shor, Y. Afek, E. Engel","doi":"10.1109/CICC.1997.606696","DOIUrl":"https://doi.org/10.1109/CICC.1997.606696","url":null,"abstract":"An IO buffer architecture is shown which provides fast output transitions as well as efficient voltage level shifting from the chip interior. The buffer contains a feedback circuit which damps ringing associated with supply bounce. Fast voltage converters are demonstrated which allow the core to operate at a lower voltage (1.8 V), without significant delay penalties on the IO (at 3.6 V). These novel circuits are important for high performance, low power applications, such as wireless DSPs.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"151 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117352157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A single chip DVB receiver for variable-rate QPSK demodulation and forward error correction 用于可变速率QPSK解调和前向纠错的单片DVB接收机
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606623
Seung-Jun Lee, J. Baek, M. Paff, Bonchul Koo, Gyu-Tae Hwang, Young-Shig Choi, Tae-Geun Kim
{"title":"A single chip DVB receiver for variable-rate QPSK demodulation and forward error correction","authors":"Seung-Jun Lee, J. Baek, M. Paff, Bonchul Koo, Gyu-Tae Hwang, Young-Shig Choi, Tae-Geun Kim","doi":"10.1109/CICC.1997.606623","DOIUrl":"https://doi.org/10.1109/CICC.1997.606623","url":null,"abstract":"This paper describes a single chip DVB compliant receiver that integrates a variable rate QPSK demodulator with a Viterbi decoder, de-interleaver, and a Reed-Solomon decoder. Using a fixed rate sampling clock it handles continuously variable symbol rate from 1 Msps to 45 Msps. Careful floor planning and flat place and route squeezed the 116,000 nand-equivalent gate design into an area of 38.8 mm/sup 2/. It has been fabricated with a 0.5 /spl mu/m CMOS TLM process. It has been extensively tested in a real-world set-up and proved fully functional.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127151585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Whole-chip ESD protection scheme for CMOS mixed-mode IC's in deep-submicron CMOS technology 基于深亚微米CMOS技术的CMOS混合模式集成电路的全片ESD保护方案
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606579
M. Ker, Chung-Yu Wu, Hun-Hsien Chang, Tain-Shun Wu
{"title":"Whole-chip ESD protection scheme for CMOS mixed-mode IC's in deep-submicron CMOS technology","authors":"M. Ker, Chung-Yu Wu, Hun-Hsien Chang, Tain-Shun Wu","doi":"10.1109/CICC.1997.606579","DOIUrl":"https://doi.org/10.1109/CICC.1997.606579","url":null,"abstract":"A whole-chip ESD protection scheme with the ESD-connection diodes and a substrate-triggering field-oxide device (STFOD) are proposed to protect mixed-mode CMOS IC's against ESD damage. The STFOD is triggered on by the substrate-triggering technique to make an area-efficient VDD-to-VSS ESD clamp circuit. The ESD-connection diodes provide the current discharging paths among the multiple separated power lines to avoid the ESD damage located at the digital-analog interface. This whole-chip ESD protection scheme has been practically verified in an L-bits DAC chip in a 0.6-/spl mu/m CMOS process with a pin-to-pin ESD robustness of above 4 KV.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126841917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A low power 170 MHz discrete-time analog FIR filter 低功率170 MHz离散时间模拟FIR滤波器
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606575
Xiaodong Wang, R. Spencer
{"title":"A low power 170 MHz discrete-time analog FIR filter","authors":"Xiaodong Wang, R. Spencer","doi":"10.1109/CICC.1997.606575","DOIUrl":"https://doi.org/10.1109/CICC.1997.606575","url":null,"abstract":"A 170 MHz analog FIR filter operating from a single 3.3 V supply is described. The design has been fabricated in the HP 1.2 /spl mu/m CMOS process and has an area of 2.35 mm by 1.97 mm including bonding pads. This 9-tap filter dissipates 70 mW when operating at 170 MHz. The multipliers are implemented using MDAC's with 6-bit resolution.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123435443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 41
A mixed-signal array processor with early vision applications 具有早期视觉应用的混合信号阵列处理器
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606629
D. A. Martin
{"title":"A mixed-signal array processor with early vision applications","authors":"D. A. Martin","doi":"10.1109/CICC.1997.606629","DOIUrl":"https://doi.org/10.1109/CICC.1997.606629","url":null,"abstract":"A programmable analog arithmetic circuit which can perform addition, subtraction, multiplication, and division at 7 bits of resolution is presented. This circuit is used as the ALU for a mixed-signal array processor designed for early vision applications. The analog arithmetic circuit enables the processor to operate with the low power and low area of a dedicated analog circuit while retaining the flexibility of a digital processor. The processor was tested with an edge detection algorithm and a sub-pixel resolution algorithm. A 1 cm square array of the mixed-signal processor cells in 0.8 /spl mu/m CMOS with a 5 V power supply would dissipate 1 W at 420 MIPS.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126335792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 42
P2Lib: process-portable library and its generation system P2Lib:进程可移植库及其生成系统
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606643
H. Onodera, A. Hirata, T. Kitamura, K. Tamaru
{"title":"P2Lib: process-portable library and its generation system","authors":"H. Onodera, A. Hirata, T. Kitamura, K. Tamaru","doi":"10.1109/CICC.1997.606643","DOIUrl":"https://doi.org/10.1109/CICC.1997.606643","url":null,"abstract":"This paper describes a process-portable library and its generation system called P2Lib. From technology parameters which characterize a fabrication process, P2Lib generates a complete set of standard cell libraries for logic synthesis, logic simulation, and layout synthesis. A distinctive feature of P2Lib is the rapid characterization of timing and power dissipation by an analytic-oriented method, as well as the accurate characterization by circuit simulation. A designer can quickly create a library under various operating conditions and process specifications, so that he can examine his design with CAD tools. The quality of generated libraries (layout and timing) are discussed and a design example with P2Lib is presented.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"12 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120845390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
A 2.5 V temperature compensated CMOS logarithmic amplifier 2.5 V温度补偿CMOS对数放大器
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606589
K. Koli, K. Halonen
{"title":"A 2.5 V temperature compensated CMOS logarithmic amplifier","authors":"K. Koli, K. Halonen","doi":"10.1109/CICC.1997.606589","DOIUrl":"https://doi.org/10.1109/CICC.1997.606589","url":null,"abstract":"A new temperature compensated low voltage current-mode CMOS logarithmic amplifier is presented. The logarithmic amplifier uses seven cascaded limiting current amplifiers for piece-wise approximation of the logarithmic function and a current peak detector for detecting signal amplitude with a dynamic range of 60 dB. The circuit uses a current reference to stabilize the temperature dependencies down to /spl plusmn/1 dB. The designed amplifier is fabricated with a 1.2 /spl mu/m CMOS process. It operates with down to a 2.2 V single supply voltage and the power consumption is 3 mW with a 2.5 V supply.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123146573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
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