{"title":"一种高线性低电压全mosfet δ - σ调制器","authors":"Y. Huang, G. Temes, H. Yoshizawa","doi":"10.1109/CICC.1997.606632","DOIUrl":null,"url":null,"abstract":"The implementation of a second-order switched-capacitor delta-sigma modulator is described. The modulator uses MOSFETs in their accumulation region as capacitors, with the input branches linearized using series compensation. It utilizes only basic digital CMOS technology and was fabricated in a 1.2 /spl mu/m process. The chip area of the modulator is about 1 mm/sup 2/. Measured results show that the modulator has a 94 dB peak S/THD, a 96 dB peak S/N and an 86 dB peak S/THD+N for a 6 kHz bandwidth with 5.4 mW power dissipation using a 3 V power supply and a 3.6 V capacitor bias voltage.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"728 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"A high-linearity low-voltage all-MOSFET delta-sigma modulator\",\"authors\":\"Y. Huang, G. Temes, H. Yoshizawa\",\"doi\":\"10.1109/CICC.1997.606632\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The implementation of a second-order switched-capacitor delta-sigma modulator is described. The modulator uses MOSFETs in their accumulation region as capacitors, with the input branches linearized using series compensation. It utilizes only basic digital CMOS technology and was fabricated in a 1.2 /spl mu/m process. The chip area of the modulator is about 1 mm/sup 2/. Measured results show that the modulator has a 94 dB peak S/THD, a 96 dB peak S/N and an 86 dB peak S/THD+N for a 6 kHz bandwidth with 5.4 mW power dissipation using a 3 V power supply and a 3.6 V capacitor bias voltage.\",\"PeriodicalId\":111737,\"journal\":{\"name\":\"Proceedings of CICC 97 - Custom Integrated Circuits Conference\",\"volume\":\"728 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-05-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of CICC 97 - Custom Integrated Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.1997.606632\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.1997.606632","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A high-linearity low-voltage all-MOSFET delta-sigma modulator
The implementation of a second-order switched-capacitor delta-sigma modulator is described. The modulator uses MOSFETs in their accumulation region as capacitors, with the input branches linearized using series compensation. It utilizes only basic digital CMOS technology and was fabricated in a 1.2 /spl mu/m process. The chip area of the modulator is about 1 mm/sup 2/. Measured results show that the modulator has a 94 dB peak S/THD, a 96 dB peak S/N and an 86 dB peak S/THD+N for a 6 kHz bandwidth with 5.4 mW power dissipation using a 3 V power supply and a 3.6 V capacitor bias voltage.
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