{"title":"Tracking of Wrist and Hand Kinematics With Ultra Low Power Wearable A-Mode Ultrasound","authors":"Giusy Spacone;Sergei Vostrikov;Victor Kartsch;Simone Benatti;Luca Benini;Andrea Cossettini","doi":"10.1109/TBCAS.2024.3465239","DOIUrl":"10.1109/TBCAS.2024.3465239","url":null,"abstract":"Ultrasound-based Hand Gesture Recognition has gained significant attention in recent years. While static gesture recognition has been extensively explored, only a few works have tackled the task of movement regression for real-time tracking, despite its importance for the development of natural and smooth interaction strategies. In this paper, we demonstrate the regression of 3 hand-wrist Degrees of Freedom (DoFs) using a lightweight, A-mode-based, truly wearable US armband featuring four transducers and WULPUS, an ultra-low-power acquisition device. We collect US data, synchronized with an optical motion capture system to establish a ground truth, from 5 subjects. We achieve state-of-the-art performance with an average root-mean-squared-error (RMSE) of <inline-formula><tex-math>$7.32^{circ}$</tex-math></inline-formula> <inline-formula><tex-math>$pm$</tex-math></inline-formula> <inline-formula><tex-math>$1.97^{circ}$</tex-math></inline-formula> and mean-absolute-error (MAE) of <inline-formula><tex-math>$5.31^{circ}$</tex-math></inline-formula> <inline-formula><tex-math>$pm$</tex-math></inline-formula> <inline-formula><tex-math>$1.42^{circ}$</tex-math></inline-formula>. Additionally, we demonstrate, for the first time, robustness with respect to transducer repositioning between acquisition sessions, achieving an average RMSE value of <inline-formula><tex-math>$11.11^{circ}$</tex-math></inline-formula> <inline-formula><tex-math>$pm$</tex-math></inline-formula> <inline-formula><tex-math>$4.14^{circ}$</tex-math></inline-formula> and a MAE of <inline-formula><tex-math>$8.46^{circ}$</tex-math></inline-formula> <inline-formula><tex-math>$pm$</tex-math></inline-formula> <inline-formula><tex-math>$3.58^{circ}$</tex-math></inline-formula>. Finally, we deploy our pipeline on a real-time low-power microcontroller, showcasing the first instance of multi-DoF regression based on A-mode US data on an embedded device, with a power consumption lower than <inline-formula><tex-math>$30 mathrm{mW}$</tex-math></inline-formula> and end-to-end latency of <inline-formula><tex-math>$approx$</tex-math></inline-formula> <inline-formula><tex-math>$80 mathrm{ms}$</tex-math></inline-formula>.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"19 3","pages":"536-548"},"PeriodicalIF":0.0,"publicationDate":"2024-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142309478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jun Wang;Seok Joo Kim;Wenxuan Wu;Jongha Lee;Henry Hinton;Rona S. Gertner;Han Sae Jung;Hongkun Park;Donhee Ham
{"title":"A Cyto-Silicon Hybrid System with On-Chip Closed-Loop Modulation","authors":"Jun Wang;Seok Joo Kim;Wenxuan Wu;Jongha Lee;Henry Hinton;Rona S. Gertner;Han Sae Jung;Hongkun Park;Donhee Ham","doi":"10.1109/TBCAS.2024.3466549","DOIUrl":"10.1109/TBCAS.2024.3466549","url":null,"abstract":"We introduce a bioelectronic interface between biological electrogenic cells and a mixed-signal CMOS integrated circuit with an array of surface electrodes, where not only is the CMOS electrode array capable of electrophysiological recording and stimulation of the cells with 1,024 recording and stimulation channels, but it can also provide low-latency artificial signal pathways from cells it records to cells it stimulates. This on-chip closed-loop modulation has an intrinsic latency less than 5 µs. To demonstrate the utility of the on-chip closed loop modulation as an artificial feedback pathway between biological cells, we develop a silicon-cardiomyocyte self-sustained oscillator with a tunable frequency to which both the relevant part of the CMOS chip and cells are locked, and also a silicon-neuron interface with a silicon inhibitory connection between neuronal cells. This line of cyto-silicon hybrid system, where the boundary between biological and semiconductor systems is blurred, may find applications in prosthesis, brain-machine interface, and fundamental biology research.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"19 3","pages":"577-589"},"PeriodicalIF":0.0,"publicationDate":"2024-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142309476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design and Implementation of Integrated Dual-Mode Pulse and Continuous-Wave Electron Paramagnetic Resonance Spectrometers","authors":"Jui-Hung Sun;Difei Wu;Peter Qin;Constantine Sideris","doi":"10.1109/TBCAS.2024.3465210","DOIUrl":"10.1109/TBCAS.2024.3465210","url":null,"abstract":"Electron paramagnetic resonance (EPR) is a powerful spectroscopic technique that allows direct detection and characterization of radicals containing unpaired electron(s). The development of portable, low-power EPR sensing modalities has the potential to significantly expand the utility of EPR in a broad range of fields, ranging from basic science to practical applications such as point-of-care diagnostics. The two major methodologies of EPR are continuous-wave (CW) EPR, where the frequency or field is swept with a constant excitation, and pulse EPR, where short pulses induce a transient signal. In this work, we present the first realization of a fully integrated pulse EPR spectrometer on-chip. The spectrometer utilizes a subharmonic direct-conversion architecture that enables an on-chip oscillator to be used as a dual-mode EPR sensing cell, capable of both CW and pulse-mode operation. An on-chip reference oscillator is used to injection-lock the sensor to form pulses and also to downconvert the pulse EPR signal. A proof-of-concept spectrometer IC with two independent sensing cells is presented, which achieves a pulse sensitivity of \u0000<inline-formula><tex-math>$4.6times 10^{9}$</tex-math></inline-formula>\u0000 spins (1000 averages) and a CW sensitivity of \u0000<inline-formula><tex-math>$2.9times 10^{9}$</tex-math></inline-formula>\u0000 spins/\u0000<inline-formula><tex-math>$sqrt{text{Hz}}$</tex-math></inline-formula>\u0000 and can be powered and controlled via a computer USB interface. The sensing cells consume as little as 2.1mW (CW mode), and the system is tunable over a wide frequency range of 12.8–14.9GHz (CW/pulse). Single-pulse free induction decay (FID), two-pulse inversion recovery, two-pulse Hahn echo, three-pulse stimulated echo, and CW experiments demonstrate the viability of the spectrometer for use in portable EPR sensing.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"18 6","pages":"1209-1219"},"PeriodicalIF":0.0,"publicationDate":"2024-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142304706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Xinguo Wang;Songyu Han;Peng Yan;Yang Lin;Chen Wang;Lei Qian;Pujia Xing;Yue Cao;Xinglei Song;Guoxing Wang;Timothy G. Constandinou;Yan Liu
{"title":"A 1024-Channel Simultaneous Electrophysiological and Electrochemical Neural Recording System With In-Pixel Digitization and Crosstalk Compensation","authors":"Xinguo Wang;Songyu Han;Peng Yan;Yang Lin;Chen Wang;Lei Qian;Pujia Xing;Yue Cao;Xinglei Song;Guoxing Wang;Timothy G. Constandinou;Yan Liu","doi":"10.1109/TBCAS.2024.3460388","DOIUrl":"10.1109/TBCAS.2024.3460388","url":null,"abstract":"Simultaneous electrophysiological and chemical recording allows for multi-modal neural instrumentation and provides insights into chemical synapses and ion channels across the cell membrane. However, inter-modal interference can hinder highly synchronized recording in large-scale systems with high temporal and spatial resolution. In this work, we propose a 1024-channel lab-on-CMOS system for dual-modal neural recording with in-pixel digitization and interference suppression. A foreground calibration scheme with tunable capacitance is implemented in-pixel to compensate for the crosstalk between electrical and chemical recording. Active pixels for both electrical and chemical modalities are designed based on a pulse width modulation (PWM) analog-to-digital conversion scheme. CMOS-compatible post-processing is implemented to realize in-pixel electrodes and chemical sensing membranes. The prototype, implemented in a 180 nm CMOS technology, occupies a total area of 33 mm<sup>2</sup> with 1024 pixels, and each unit pixel includes one electrical recording site and two chemical recording sites, with dimensions of 150 <inline-formula><tex-math>$mu$</tex-math></inline-formula>m <inline-formula><tex-math>$times$</tex-math></inline-formula> 130 <inline-formula><tex-math>$mu$</tex-math></inline-formula>m. The total system power consumption is 19.68 mW at a frame rate of 9k and 3k for electrical and chemical imaging respectively. The <italic>in-vitro</i> experiment demonstrated the concurrent high density electrophysilogical and electrochemical recording with sub millisecond temporal resolution.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"19 3","pages":"549-561"},"PeriodicalIF":0.0,"publicationDate":"2024-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142251954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jisan Ahn;Hyun-Su Lee;Kyeongho Eom;Woojoong Jung;Hyung-Min Lee
{"title":"A 13.56-MHz 93.5%-Efficiency Optimal On/Off Timing Tracking Active Rectifier With Digital Feedback-Based Adaptive Delay Control","authors":"Jisan Ahn;Hyun-Su Lee;Kyeongho Eom;Woojoong Jung;Hyung-Min Lee","doi":"10.1109/TBCAS.2024.3457848","DOIUrl":"10.1109/TBCAS.2024.3457848","url":null,"abstract":"This paper presents an adaptive active rectifier with digital feedback delay controllers (DFDC) which quickly tracks optimal on/off timing against input voltage and load variations. To efficiently generate the on/off transition, the proposed active rectifier adopts dynamically controlled coarse/fine delay lines rather than using conventional power-hungry static comparators, while removing the risk of unwanted multiple driving pulses to pass transistors. DFDC conducts the dual-loop digital feedback to independently adjust on/off timing with high-speed 13.56-MHz loop bandwidth, improving the voltage conversion ratio (VCR) and power conversion efficiency (PCE). DFDC can enable real-time power-saving mode control that automatically masks clock-toggling to non-essential blocks to minimize dynamic power loss while driving power transistors. To validate the efficacy of the proposed adaptive rectifier during digital feedback and settling procedures, experiments were carried out with 0.25 μm CMOS prototype at the carrier frequency of 13.56-MHz, input voltages between 1.7 and 2.6 V, and load ranges from 0.33 to 2.2 kΩ. The proposed active rectifier employing DFDC achieves a peak PCE of 93.5% and the peak VCR of 96.3% at the output power of 12.52 mW and 2.02 mW, respectively.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"19 3","pages":"562-576"},"PeriodicalIF":0.0,"publicationDate":"2024-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142195022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Closed-Loop Implantable Neurostimulators for Individualized Treatment of Intractable Epilepsy: A Review of Recent Developments, Ongoing Challenges, and Future Opportunities","authors":"Hossein Kassiri;Abdul Muneeb;Rojin Salahi;Alireza Dabbaghian","doi":"10.1109/TBCAS.2024.3456825","DOIUrl":"10.1109/TBCAS.2024.3456825","url":null,"abstract":"Driven by its proven therapeutic efficacy in treating movement disorders and psychiatric conditions, neurostimulation has emerged as a promising intervention for intractable epilepsy. Researchers envision an advanced implantable device capable of long-term neuronal monitoring, high spatio-temporal resolution data processing, and timely responsive neurostimulation upon seizure detection. However, the stringent energy constraints of implantable devices and significant inter-patient variability in neural activity pose substantial challenges and opportunities for biomedical circuits and systems researchers. For seizure detection, various ASIC solutions employing both deterministic and data-driven algorithms have been developed. These solutions leverage a subset of numerous signal features (spanning time and frequency domains) and classifiers (such as SVMs, DNNs, SNNs) to achieve notable success in terms of detection accuracy, latency, and energy efficiency. Implementations vary widely in computational approaches (digital, mixed-signal, analog, spike-based), training strategies (online versus offline), and application targets (patient-specific versus cross-patient). In terms of treatment, recent efforts have focused on the personalization of stimulation waveforms to enhance therapeutic efficacy. This personalization faces complex challenges, including a limited understanding of how stimulation parameters influence neuronal activity, the lack of a comprehensive brain model to capture its intricate electrochemical dynamics, and recording neural signals in the presence of stimulation artifacts. This review provides a comprehensive overview of the field, detailing the foundational principles, recent advancements, and ongoing challenges in enhancing the diagnostic accuracy, treatment efficacy, and energy efficiency of implantable patient-optimized neurostimulators. We also discuss potential future directions, emphasizing the need for standardized performance metrics, advanced computational models, and adaptive stimulation protocols to realize the full potential of this transformative technology.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"18 6","pages":"1268-1295"},"PeriodicalIF":0.0,"publicationDate":"2024-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142195024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Lan Mei;Thorir Mar Ingolfsson;Cristian Cioflan;Victor Kartsch;Andrea Cossettini;Xiaying Wang;Luca Benini
{"title":"An Ultra-Low Power Wearable BMI System With Continual Learning Capabilities","authors":"Lan Mei;Thorir Mar Ingolfsson;Cristian Cioflan;Victor Kartsch;Andrea Cossettini;Xiaying Wang;Luca Benini","doi":"10.1109/TBCAS.2024.3457522","DOIUrl":"10.1109/TBCAS.2024.3457522","url":null,"abstract":"Driven by the progress in efficient embedded processing, there is an accelerating trend toward running machine learning models directly on wearable Brain-Machine Interfaces (BMIs) to improve portability and privacy and maximize battery life. However, achieving low latency and high classification performance remains challenging due to the inherent variability of electroencephalographic (EEG) signals across sessions and the limited onboard resources. This work proposes a comprehensive BMI workflow based on a CNN-based Continual Learning (CL) framework, allowing the system to adapt to inter-session changes. The workflow is deployed on a wearable, parallel ultra-low power BMI platform (BioGAP). Our results based on two in-house datasets, Dataset A and Dataset B, show that the CL workflow improves average accuracy by up to 30.36% and 10.17%, respectively. Furthermore, when implementing the continual learning on a Parallel Ultra-Low Power (PULP) microcontroller (GAP9), it achieves an energy consumption as low as 0.45 mJ per inference and an adaptation time of only 21.5 ms, yielding around 25 h of battery life with a small 100 mAh, 3.7 V battery on BioGAP. Our setup, coupled with the compact CNN model and on-device CL capabilities, meets users’ needs for improved privacy, reduced latency, and enhanced inter-session performance, offering good promise for smart embedded real-world BMIs.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"19 3","pages":"511-522"},"PeriodicalIF":0.0,"publicationDate":"2024-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142195023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Matteo Antonio Scrugli;Gianluca Leone;Paola Busia;Luigi Raffo;Paolo Meloni
{"title":"Real-Time sEMG Processing With Spiking Neural Networks on a Low-Power 5K-LUT FPGA","authors":"Matteo Antonio Scrugli;Gianluca Leone;Paola Busia;Luigi Raffo;Paolo Meloni","doi":"10.1109/TBCAS.2024.3456552","DOIUrl":"10.1109/TBCAS.2024.3456552","url":null,"abstract":"The accurate modeling of hand movement based on the analysis of surface electromyographic (sEMG) signals offers exciting opportunities for the development of complex prosthetic devices and human-machine interfaces, moving from discrete gesture recognition, towards continuous movement tracking. In this study, we present two solutions for real-time sEMG processing, based on lightweight Spiking Neural Networks (SNNs) and efficiently implemented on a Lattice iCE40-UltraPlus FPGA, especially suitable for low-power applications. We first assess the performance in the discrete finger gesture recognition task, considering as a reference the NinaPro DB5 dataset, and demonstrating an accuracy of 83.17% in the classification of twelve different finger gestures. We also consider the more challenging problem of continuous finger force modeling, referencing the Hyser dataset for finger tracking during independent extension and contraction exercises. The assessment reveals a correlation of up to 0.875 with the ground-truth forces. Our systems take advantage of SNNs’ inherent efficiency and, dissipating 11.31 mW in active mode, consume 44.6 µJ for a gesture recognition classification and 1.19 µJ for a force modeling inference. Considering dynamic power-consumption management and the introduction of idle periods, average power drops to 1.84 mW and 3.69 mW for these respective tasks.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"19 1","pages":"68-81"},"PeriodicalIF":0.0,"publicationDate":"2024-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10669772","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142195025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"NEXUS: A 28nm 3.3pJ/SOP 16-Core Spiking Neural Network With a Diamond Topology for Real-Time Data Processing","authors":"Maryam Sadeghi;Yasser Rezaeiyan;Dario Fernandez Khatiboun;Sherif Eissa;Federico Corradi;Charles Augustine;Farshad Moradi","doi":"10.1109/TBCAS.2024.3452635","DOIUrl":"10.1109/TBCAS.2024.3452635","url":null,"abstract":"The realization of brain-scale spiking neural networks (SNNs) is impeded by power constraints and low integration density. To address these challenges, multi-core SNNs are utilized to emulate numerous neurons with high energy efficiency, where spike packets are routed through a network-on-chip (NoC). However, the information can be lost in the NoC under high spike traffic conditions, leading to performance degradation. This work presents NEXUS, a 16-core SNN with a diamond-shaped NoC topology fabricated in 28-nm CMOS technology. It integrates 4096 leaky integrate-and-fire (LIF) neurons with 1M 4-bit synaptic weights, occupying an area of 2.16 mm<sup>2</sup>. The proposed NoC architecture is scalable to any network size, ensuring no data loss due to contending packets with a maximum routing latency of 5.1<inline-formula><tex-math>$mu$</tex-math></inline-formula>s for 16 cores. The proposed congestion management method eliminates the need for FIFO in routers, resulting in a compact router footprint of 0.001 mm<sup>2</sup>. The proposed neurosynaptic core allows for increasing the processing speed by up to 8.5<inline-formula><tex-math>$times$</tex-math></inline-formula> depending on input sparsity. The SNN achieves a peak throughput of 4.7 GSOP/s at 0.9 V, consuming a minimum energy per synaptic operation (SOP) of 3.3 pJ at 0.55 V. A 4-layer feed-forward network is mapped onto the chip, classifying MNIST digits with 92.3% accuracy at 8.4K-classification/s and consuming 2.7-<inline-formula><tex-math>$mu$</tex-math></inline-formula>J/classification. Additionally, an audio recognition task mapped onto the chip achieves 87.4% accuracy at 215-<inline-formula><tex-math>$mu$</tex-math></inline-formula>J/classification.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"19 3","pages":"523-535"},"PeriodicalIF":0.0,"publicationDate":"2024-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142116468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"GCOC: A Genome Classifier-On-Chip Based on Similarity Search Content Addressable Memory","authors":"Yuval Harary;Paz Snapir;Shir Siman Tov;Chen Kruphman;Eyal Rechef;Zuher Jahshan;Esteban Garzón;Leonid Yavits","doi":"10.1109/TBCAS.2024.3449788","DOIUrl":"10.1109/TBCAS.2024.3449788","url":null,"abstract":"GCOC is a genome classification system-on-chip (SoC) that classifies genomes by <inline-formula><tex-math>$k$</tex-math></inline-formula>-mer matching, an approach that divides a DNA query sequence into a set of short DNA fragments of size <italic>k</i>, which are searched in a reference genome database, with the underlying assumption that sequenced DNA reads of the same organism (or its close variants) share most of such <inline-formula><tex-math>$k$</tex-math></inline-formula>-mers. At the core of GCOC is a similarity, or approximate search-capable Content Addressable Memory (SAS-CAM), which in addition to exact match, also supports approximate, or Hamming distance tolerant search. Classification operation is controlled by an embedded RISC-V processor. GCOC classification platform was designed and manufactured in a commercial 65nm process. We conduct a thorough analysis of GCOC classification efficiency as well as its performance, silicon area, and power consumption using silicon measurements. GCOC classifies 769.2K short DNA reads/sec. The silicon area of GCOC SoC is 3.12 <inline-formula><tex-math>$mathrm{mm}^{2}$</tex-math></inline-formula> and its power consumption is 1.27 <inline-formula><tex-math>$mathrm{mW}$</tex-math></inline-formula>. We envision GCOC deployed as a field (for example at points of care) portable classifier where the classification is required to be real-time, easy to operate and energy efficient.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"19 3","pages":"484-495"},"PeriodicalIF":0.0,"publicationDate":"2024-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142086424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}