IEEE transactions on biomedical circuits and systems最新文献

{"title":"A 1.11 mm2 IVUS SoC with ±50°-Range Plane Wave Transmit Beamforming at 40 MHz.","authors":"Xitie Zhang, Evren F Arkan, Coskun Tekes, M Sait Kilinc, Tzu-Han Wang, F Levent Degertekin, Shaolan Li","doi":"10.1109/TBCAS.2024.3409162","DOIUrl":"https://doi.org/10.1109/TBCAS.2024.3409162","url":null,"abstract":"<p><p>Intravascular ultrasound (IVUS) imaging catheters are significant tools for cardiovascular interventions, and their use can be expanded by realizing IVUS imaging guidewires and microcatheters. The miniaturization of these devices creates challenges in SNR due to the need for higher frequencies to provide adequate resolution. An integrated IVUS system with transmit beamforming can mitigate these limitations. This work presents the first practical highly integrated system-on-a-chip (SoC) with plane wave transmit beamforming at 40 MHz for IVUS on guidewire or microcatheters. The front-end circuitry has a 20-channel ultrasound transmitter (Tx) and receiver (Rx) array interfaced with a capacitive micromachined ultrasound transducer (CMUT) array. During each firing, all 20 Tx are excited with the same analog delay with respect to each other, which can be continuously adjusted between ~0 and 10 ns in two directions, generating a steerable plane wave in a range of ±/-50° for a phased array at 40 MHz. The unit delays are generated via a voltage-controlled delay line (VCDL), which only needs two external controls, one tuning the unit delay and the other determining the steering direction. The SoC is fabricated using a 180-nm high-voltage (HV) CMOS process and features a slender active area of 0.3 mm × 3.7 mm. The proposed SoC consumes 31.3 mW during the receiving mode. The beamformer's functionality and the SoC's overall performance were validated through acoustic characterization and imaging experiments.</p>","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"PP ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141249075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Energy-Efficient Spectral Analysis of ECGs on Resource Constrained IoT Devices.","authors":"Charalampos Eleftheriadis, Georgios Karakonstantis","doi":"10.1109/TBCAS.2024.3406520","DOIUrl":"https://doi.org/10.1109/TBCAS.2024.3406520","url":null,"abstract":"<p><p>Power spectral analysis (PSA) is one of the most popular and insightful methods, currently employed in several biomedical applications, aiming to identify and monitor various health related conditions. Among the most common applications of PSA is heart rate variability (HRV) analysis, which allows the extraction of further insights compared with conventional time-domain methods. Unfortunately, existing PSA approaches exhibit high computational complexity, hindering their execution on power-constrained embedded internet of things (IoT) devices. Such IoT devices are increasingly used for monitoring various conditions mainly by processing the input signals in the less complex time-domain. In this paper, a new low-complexity PSA system based on fast Gaussian gridding (FGG) is proposed, which can be used to calculate the Lomb-Scargle periodogram (LSP) of a non-uniformly spaced RR tachogram. The proposed approach is implemented on a popular ARM Cortex-M4 based embedded system, which is widely used in common wearables, and compared with conventional LSP-based approaches. Utilizing this experimental setup, a meticulous analysis is performed in terms of power, performance and quality under different operational settings, such as the total input/output samples, precision of computations, computer arithmetic (floating/fixed-point), and clock frequency. The experimental results show that the proposed FGG-based LSP approach, when specifically optimized for the targeted embedded device, outperforms existing approaches by up-to 92.99% and 91.70% in terms of energy consumption and total execution time respectively, with minimal accuracy loss.</p>","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"PP ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141177137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Ultra-Compact Pulse Charger for Lithium Polymer Battery with Simple Built-in Resistance Compensation in Biomedical Applications.","authors":"Yemin Kim, Junhyuck Lee, Byunghun Lee","doi":"10.1109/TBCAS.2024.3401846","DOIUrl":"https://doi.org/10.1109/TBCAS.2024.3401846","url":null,"abstract":"Active implantable medical devices (AIMDs) rely on batteries for uninterrupted operation and patient safety. Therefore, it is critical to ensure battery safety and longevity. To achieve this, constant current/constant voltage (CC/CV) methods have been commonly used and research has been conducted to compensate for the effects of built-in resistance (BIR) of batteries. However, conventional CC/CV methods may pose the risk of lithium plating. Furthermore, conventional compensation methods for BIR require external components, complex algorithms, or large chip sizes, which inhibit the miniaturization and integration of AIMDs. To address this issue, we have developed a pulse charger that utilizes pulse current to ensure battery safety and facilitate easy compensation for BIR. A comparison with previous research on BIR compensation shows that our approach achieves the smallest chip size of 0.0062 mm2 and the lowest system complexity using 1-bit ADC. In addition, we have demonstrated a reduction in charging time by at least 44.4% compared to conventional CC/CV methods, validating the effectiveness of our system's BIR compensation. The compact size and safety features of the proposed charging system make it promising for AIMDs, which have space-constrained environments.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"55 25","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140970496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Voltage-Assist 16-Channel Electrochemical Biosensor with Linearity Compensation.","authors":"Yifei Fan, Dongmin Shi, Yanhang Chen, Qifeng Huang, Siji Huang, Qiwei Zhao, Saqib Mohamad, Jie Yuan","doi":"10.1109/TBCAS.2024.3401784","DOIUrl":"https://doi.org/10.1109/TBCAS.2024.3401784","url":null,"abstract":"<p><p>Large capacitive loading of electrodes induces massive error current and imperfect settling in the electrochemical signal acquisition process, leading to inaccurate acquisition results. To efficiently mitigate this inaccuracy, this paper presents a current-and-voltage dual-mode acquisition technique in which a voltage front-end (VFE) is employed to acquire the electrode voltage error and compensate the nonlinearity induced by the electrode capacitive loading. Therefore, the gain and bandwidth requirements of the current front end (CFE) can be relaxed to reduce the complexity and power consumption. With a relieved gain requirement, an inverter-based capacitive trans-impedance amplifier (IB-CTIA) is adopted to boost the input transconductance for low-noise design. By reusing the supply current, the IB-CTIA effectively achieves a low input-referred current noise of 3.9 pA_rms and a dynamic range (DR) of 126 dB with only 18-μW static power. The prototype chip is fabricated in a 180-nm CMOS process. Interleukin-6 immunoassays (IL-6) are implemented to verify the chip's performance. With the proposed nonlinear error compensation, the correlation coefficient of the detection result is improved from 0.951 to 0.980 and the limit of detection (LoD) is reduced from 8.31 pg/mL to 6.90 pg/mL.</p>","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"PP ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140946729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Power-and-Area-Efficient Channel-Interleaved Neural Signal Processor for Wireless Brain-Computer Interfaces with Unsupervised Spike Sorting.","authors":"Zichen Hu, Zhining Zhou, Hongming Lyu","doi":"10.1109/TBCAS.2024.3395353","DOIUrl":"10.1109/TBCAS.2024.3395353","url":null,"abstract":"<p><p>Next generation of wireless brain-computer-interface (BCI) devices require dedicated neural signal processors (NSPs) to extract key neurological information while operating within given power consumption and transmission bandwidth limits. Spike detection and clustering are important signal processing steps in neurological research and clinical applications. Computational-friendly spike detection and feature extraction algorithms are first systematically evaluated in this work. The nonlinear energy operator (NEO) and the first-and-second-derivative (FSDE) together with the 'perturbed' K-mean clustering achieve the highest accuracy performance. An NSP ASIC is implemented in a channel-interleaved architecture and the folding ratio of 16 leads to the minimum power-and-area product. As the result, the NSP consumes 2-μW power consumption and occupies 0.0057 mm2 for each channel in a 65-nm CMOS technology. The proposed system achieves the unsupervised spike classification accuracy of 92% and a data-rate reduction of 98.3%, showing the promise for realizing high-channel-count wireless BCIs.</p>","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"PP ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140905047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"BrainFuseNet: Enhancing Wearable Seizure Detection Through EEG-PPG-Accelerometer Sensor Fusion and Efficient Edge Deployment","authors":"Thorir Mar Ingolfsson;Xiaying Wang;Upasana Chakraborty;Simone Benatti;Adriano Bernini;Pauline Ducouret;Philippe Ryvlin;Sándor Beniczky;Luca Benini;Andrea Cossettini","doi":"10.1109/TBCAS.2024.3395534","DOIUrl":"10.1109/TBCAS.2024.3395534","url":null,"abstract":"This paper introduces \u0000<sc>BrainFuseNet</small>\u0000, a novel lightweight seizure detection network based on the sensor fusion of electroencephalography (EEG) with photoplethysmography (PPG) and accelerometer (ACC) signals, tailored for low-channel count wearable systems. \u0000<sc>BrainFuseNet</small>\u0000 utilizes the Sensitivity-Specificity Weighted Cross-Entropy (SSWCE), an innovative loss function incorporating sensitivity and specificity, to address the challenge of heavily unbalanced datasets. The \u0000<sc>BrainFuseNet</small>\u0000-SSWCE approach successfully detects \u0000<inline-formula><tex-math>$93.5%$</tex-math></inline-formula>\u0000 seizure events on the CHB-MIT dataset (\u0000<inline-formula><tex-math>$76.34%$</tex-math></inline-formula>\u0000 sample-based sensitivity), for EEG-based classification with only four channels. On the PEDESITE dataset, we demonstrate a sample-based sensitivity and false positive rate of \u0000<inline-formula><tex-math>$60.66%$</tex-math></inline-formula>\u0000 and \u0000<inline-formula><tex-math>$1.18$</tex-math></inline-formula>\u0000 FP/h, respectively, when considering EEG data alone. Additionally, we demonstrate that integrating PPG signals increases the sensitivity to \u0000<inline-formula><tex-math>$61.22%$</tex-math></inline-formula>\u0000 (successfully detecting \u0000<inline-formula><tex-math>$92%$</tex-math></inline-formula>\u0000 seizure events) while decreasing the number of false positives to \u0000<inline-formula><tex-math>$1.0$</tex-math></inline-formula>\u0000 FP/h. Finally, when ACC data are also considered, the sensitivity increases to \u0000<inline-formula><tex-math>$64.28%$</tex-math></inline-formula>\u0000 (successfully detecting \u0000<inline-formula><tex-math>$95%$</tex-math></inline-formula>\u0000 seizure events) and the number of false positives drops to only \u0000<inline-formula><tex-math>$0.21$</tex-math></inline-formula>\u0000 FP/h for sample-based estimations, with less than one false alarm per day when considering event-based estimations. \u0000<sc>BrainFuseNet</small>\u0000 is resource-friendly and well-suited for implementation on low-power embedded platforms, and we evaluate its performance on GAP9, a state-of-the-art parallel ultra-low power (PULP) microcontroller for tiny Machine Learning applications on wearables. The implementation on GAP9 achieves an energy efficiency of \u0000<inline-formula><tex-math>$21.43$</tex-math></inline-formula>\u0000 GMAC/s/W, with an energy consumption per inference of only \u0000<inline-formula><tex-math>$0.11$</tex-math></inline-formula>\u0000 mJ at high performance (\u0000<inline-formula><tex-math>$412.54$</tex-math></inline-formula>\u0000 MMAC/s). The \u0000<sc>BrainFuseNet</small>\u0000-SSWCE method demonstrates effective and accurate seizure detection on heavily imbalanced datasets while achieving state-of-the-art performance in the false positive rate and being well-suited for deployment on energy-constrained edge devices.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"18 4","pages":"720-733"},"PeriodicalIF":0.0,"publicationDate":"2024-04-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10511055","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140827553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"HybMED: A Hybrid Neural Network Training Processor With Multi-Sparsity Exploitation for Internet of Medical Things","authors":"Shiqi Zhao;Chuanqing Wang;Chaoming Fang;Fengshi Tian;Jie Yang;Mohamad Sawan","doi":"10.1109/TBCAS.2024.3389875","DOIUrl":"10.1109/TBCAS.2024.3389875","url":null,"abstract":"Cloud-based training and edge-based inference modes for Artificial Intelligence of Medical Things (AIoMT) applications suffer from accuracy degradation due to physiological signal variations among patients. On-chip learning can overcome this issue by online adaptation of neural network parameters for user-specific tasks. However, existing on-chip learning processors have limitations in terms of versatility, resource utilization, and energy efficiency. We propose HybMED, which is a novel neural signal processor that supports on-chip hybrid neural network training using a composite direct feedback alignment-based paradigm. HybMED is suitable for general-purpose health monitoring AIoMT devices. It improves resource utilization and area efficiency by the reconfigurable homogeneous core with heterogeneous data flow and enhances energy efficiency by exploiting sparsity at different granularities. The chip was fabricated by TSMC 40nm process and tested in multiple physiological signal processing tasks, demonstrating an average improvement in accuracy of 41.16% following online few-shot learning. The chip demonstrates an area efficiency of 1.17 GOPS/mm\u0000<inline-formula><tex-math>${}^{2}$</tex-math></inline-formula>\u0000 and an energy efficiency of 1.58 TOPS/W. Compared to the previous state-of-the-art physiological signal processors with on-chip learning, the chip achieves a 65\u0000<inline-formula><tex-math>$times$</tex-math></inline-formula>\u0000 improvement in area efficiency and 1.48\u0000<inline-formula><tex-math>$times$</tex-math></inline-formula>\u0000 improvement in energy efficiency, respectively.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"18 5","pages":"1178-1189"},"PeriodicalIF":0.0,"publicationDate":"2024-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140617621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High Precision Ping-Pong Auto-Zeroed Lock-in Fluorescence Photometry Sensor","authors":"Vahid Khojasteh Lazarjan;Marie-Ève Crochetière;Mehdi Noormohammadi Khiarak;Saeed Ghaneei Aarani;Seyedeh Nazila Hosseini;Gabriel Gagnon-Turcotte;Pierre Marquet;Benoit Gosselin","doi":"10.1109/TBCAS.2024.3388569","DOIUrl":"10.1109/TBCAS.2024.3388569","url":null,"abstract":"This paper presents a high-precision CMOS fluorescence photometry sensor using a novel lock-in amplification scheme based on switched-biasing and ping-pong auto-zeroing techniques. The CMOS sensor includes two photodiodes and a lock-in amplifier (LIA) operating at 1 kHz. The LIA comprises a differential low-noise amplifier using a novel switched-biasing ping-pong auto-zeroed scheme, an automatic phase aligner, a programmable gain amplifier, a band-pass filter, a mixer, and an output low-pass filter. The design is fabricated in 0.18-µm CMOS process, and the measurement shows that the LIA can retrieve noisy input signals with a dynamic reserve of 42 dB, while consuming only 0.7 mW from a 1.8 V supply voltage. The measured results show that the LIA can detect a wide range of incident light power from 8 nW to 24 µW. The proposed design is encapsulated in a 3D-printed housing allowing for real-time \u0000<italic>in vitro</i>\u0000 biomarker detection. This ambulatory platform uses an LED and a fiber optic to convey the excitation light to the sample and retrieve the fluorescence signal. Experiments with a beads solution diluted in PBS demonstrate that the sensor has a sensitivity of 1:100 k. Experimental results obtained \u0000<italic>in vitro</i>\u0000 with NIH3T3 mouse cells tagged with membrane dye show the ability of the prototype to detect different densities of cell culture. The portable prototype, which includes optical filters and a small 30 mm × 36 mm × 30 mm printed circuit board enclosed inside the 3D-printed housing, consumes 36.7 mW and weighs 120 g.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"18 5","pages":"1140-1155"},"PeriodicalIF":0.0,"publicationDate":"2024-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140617875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Operant Conditioning Neuromorphic Circuit With Addictiveness and Time Memory for Automatic Learning","authors":"Gang Dou;Wenhai Guo;Lingtong Kong;Junwei Sun;Mei Guo;Shiping Wen","doi":"10.1109/TBCAS.2024.3388673","DOIUrl":"10.1109/TBCAS.2024.3388673","url":null,"abstract":"Most operant conditioning circuits predominantly focus on simple feedback process, few studies consider the intricacies of feedback outcomes and the uncertainty of feedback time. This paper proposes a neuromorphic circuit based on operant conditioning with addictiveness and time memory for automatic learning. The circuit is mainly composed of hunger output module, neuron module, excitement output module, memristor-based decision module, and memory and feedback generation module. In the circuit, the process of output excitement and addiction in stochastic feedback is achieved. The memory of interval between the two rewards is formed. The circuit can adapt to complex scenarios with these functions. In addition, hunger and satiety are introduced to realize the interaction between biological behavior and exploration desire, which enables the circuit to continuously reshape its memories and actions. The process of operant conditioning theory for automatic learning is accomplished. The study of operant conditioning can serve as a reference for more intelligent brain-inspired neural systems.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"18 5","pages":"1166-1177"},"PeriodicalIF":0.0,"publicationDate":"2024-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140568263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"SC-PLR: An Approximate Spiking Neural Network Accelerator With On-Chip Predictive Learning Rule","authors":"Wei Liu;Shanlin Xiao;Yue Liu;Zhiyi Yu","doi":"10.1109/TBCAS.2024.3385235","DOIUrl":"10.1109/TBCAS.2024.3385235","url":null,"abstract":"The brain's ability to anticipate future events is crucial for intelligent behavior. However, when deploying the capability to edge devices, there are huge challenges in terms of resources and power consumption. The main obstacle is the state-of-the-art neuromorphic hardware with Spike Timing Dependent Plasticity (STDP) learning rule requires significant computation for synaptic weight updates and memory to store intermediate synaptic weights. In this paper, we proposed an approximate Spiking Neural Network (SNN) accelerator with on-chip Predictive Learning Rule (PLR), which is a biological behavior observed in the brain, named SC-PLR. In SC-PLR, the principles of predictive processing are extended to enable neurons to learn temporal sequences and anticipate future events with minimum synaptic weight updates, while stochastic computing is leveraged to balance the hardware cost, energy efficiency, and accuracy. Simulation results demonstrate that PLR-based SNNs effectively enable adaptive and anticipatory behavior in robotics and decision-making scenarios. Additionally, FPGA implementation results show that the proposed SC-PLR outperforms state-of-the-art STDP-based SNN designs in terms of resources and power consumption. Specifically, our design achieves significant resource savings, including 77.3% Look-Up Table (LUT), 79.4% Flip-Flop (FF), and 56.4% Block RAM (BRAM) resources, and power consumption reduction by 32%.\u0000<xref>¹</xref>\u0000<fn><label>¹</label><p>The code is available at <uri>https://github.com/lucy-weizi/SC-PLR</uri>.</p></fn>","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"18 5","pages":"1156-1165"},"PeriodicalIF":0.0,"publicationDate":"2024-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140567960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}